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soc/intel/common/fast_spi: support caching bios in ramstage 

After the MTRR solution has been calculated provide a way
for code to call the same function, fast_spi_cache_bios_region(),
in all stages. This is accomplished by using the ramstage
temporary MTRR support.

Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin 2017-06-08 10:52:58 -05:00
parent ea0497c786
commit 0b34fc6f54
2 changed files with 17 additions and 8 deletions
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21
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -179,14 +179,10 @@ size_t fast_spi_get_bios_region(size_t *bios_size)
void fast_spi_cache_bios_region(void)
{
int mtrr;
size_t bios_size;
uint32_t alignment;
mtrr = get_free_var_mtrr();
if (mtrr == -1)
return;
const int type = MTRR_TYPE_WRPROT;
uintptr_t base;
/* Only the IFD BIOS region is memory mapped (at top of 4G) */
fast_spi_get_bios_region(&bios_size);
@ -197,7 +193,18 @@ void fast_spi_cache_bios_region(void)
/* Round to power of two */
alignment = 1 << (log2_ceil(bios_size));
bios_size = ALIGN_UP(bios_size, alignment);
set_var_mtrr(mtrr, 4ULL*GiB - bios_size, bios_size, MTRR_TYPE_WRPROT);
base = 4ULL*GiB - bios_size;
if (ENV_RAMSTAGE) {
mtrr_use_temp_range(base, bios_size, type);
} else {
int mtrr = get_free_var_mtrr();
if (mtrr == -1)
return;
set_var_mtrr(mtrr, base, bios_size, type);
}
}
/*

4
src/soc/intel/common/block/include/intelblocks/fast_spi.h
View File

@ -57,7 +57,9 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data);
*/
size_t fast_spi_get_bios_region(size_t *bios_size);
/*
* Cache the memory-mapped BIOS region as write-protect type.
* Cache the memory-mapped BIOS region as write-protect type. In ramstage
* this function needs to be called after the final MTRR solution has been
* calculated.
*/
void fast_spi_cache_bios_region(void);
/*