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sb/intel: Remove inexistent references to IDE controller 

This device doesn't exist on these southbridges.

Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-10 13:02:20 +02:00
parent 1d68d6d14d
commit 0b3512b495
3 changed files with 3 additions and 6 deletions
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3
src/southbridge/intel/bd82x6x/pch.h
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@ -155,8 +155,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define LGMR 0x98 /* LPC Generic Memory Range */ #define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */
/* PCI Configuration Space (D31:F1): IDE */ /* PCI Configuration Space (D31:F2): SATA */
#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_TIM_PRI 0x40 /* IDE timings, primary */

3
src/southbridge/intel/ibexpeak/pch.h
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@ -148,8 +148,7 @@ void pch_enable(struct device *dev);
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
/* PCI Configuration Space (D31:F1): IDE */ /* PCI Configuration Space (D31:F2): SATA */
#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define INTR_LN 0x3c #define INTR_LN 0x3c

3
src/southbridge/intel/lynxpoint/pch.h
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@ -212,8 +212,7 @@ void mainboard_config_rcba(void);
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LGMR 0x98 /* LPC Generic Memory Range */ #define LGMR 0x98 /* LPC Generic Memory Range */
/* PCI Configuration Space (D31:F1): IDE */ /* PCI Configuration Space (D31:F2): SATA */
#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
#define INTR_LN 0x3c #define INTR_LN 0x3c