intel/pci_devs: Regroup PCI xx_DEVID entries
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
3d4923d85a
commit
0b4298c242
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@ -21,131 +21,132 @@
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/* SoC transaction router */
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#define SOC_DEV 0x0
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#define SOC_FUNC 0
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# define SOC_DEVID 0x0f00
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/* Graphics and Display */
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#define GFX_DEV 0x2
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#define GFX_FUNC 0
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# define GFX_DEVID 0x0f31
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/* SDIO Port */
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#define SDIO_DEV 0x11
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#define SDIO_FUNC 0
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# define SDIO_DEVID 0x0f15
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/* SD Port */
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#define SD_DEV 0x12
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#define SD_FUNC 0
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# define SD_DEVID 0x0f16
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/* SATA */
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#define SATA_DEV 0x13
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#define SATA_FUNC 0
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#define IDE1_DEVID 0x0f20
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#define IDE2_DEVID 0x0f21
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#define AHCI1_DEVID 0x0f22
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#define AHCI2_DEVID 0x0f23
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/* xHCI */
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#define XHCI_DEV 0x14
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#define XHCI_FUNC 0
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# define XHCI_DEVID 0x0f35
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/* LPE Audio */
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#define LPE_DEV 0x15
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#define LPE_FUNC 0
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# define LPE_DEVID 0x0f28
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/* MMC Port */
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#define MMC_DEV 0x17
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#define MMC_FUNC 0
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# define MMC_DEVID 0x0f50
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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# define SIO_DMA1_DEV SIO1_DEV
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# define SIO_DMA1_FUNC 0
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# define SIO_DMA1_DEVID 0x0f40
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# define I2C1_DEV SIO1_DEV
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# define I2C1_FUNC 1
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# define I2C1_DEVID 0x0f41
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# define I2C2_DEV SIO1_DEV
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# define I2C2_FUNC 2
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# define I2C2_DEVID 0x0f42
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# define I2C3_DEV SIO1_DEV
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# define I2C3_FUNC 3
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# define I2C3_DEVID 0x0f43
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# define I2C4_DEV SIO1_DEV
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# define I2C4_FUNC 4
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# define I2C4_DEVID 0x0f44
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# define I2C5_DEV SIO1_DEV
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# define I2C5_FUNC 5
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# define I2C5_DEVID 0x0f45
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# define I2C6_DEV SIO1_DEV
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# define I2C6_FUNC 6
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# define I2C6_DEVID 0x0f46
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# define I2C7_DEV SIO1_DEV
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# define I2C7_FUNC 7
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# define I2C7_DEVID 0x0f47
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/* Trusted Execution Engine */
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#define TXE_DEV 0x1a
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#define TXE_FUNC 0
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# define TXE_DEVID 0x0f18
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/* HD Audio */
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#define HDA_DEV 0x1b
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#define HDA_FUNC 0
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# define HDA_DEVID 0x0f04
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/* PCIe Ports */
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#define PCIE_DEV 0x1c
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# define PCIE_PORT1_DEV PCIE_DEV
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# define PCIE_PORT1_FUNC 0
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# define PCIE_PORT1_DEVID 0x0f48
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# define PCIE_PORT2_DEV PCIE_DEV
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# define PCIE_PORT2_FUNC 1
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# define PCIE_PORT2_DEVID 0x0f4a
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# define PCIE_PORT3_DEV PCIE_DEV
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# define PCIE_PORT3_FUNC 2
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# define PCIE_PORT3_DEVID 0x0f4c
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# define PCIE_PORT4_DEV PCIE_DEV
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# define PCIE_PORT4_FUNC 3
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# define PCIE_PORT4_DEVID 0x0f4e
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/* EHCI */
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#define EHCI_DEV 0x1d
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#define EHCI_FUNC 0
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# define EHCI_DEVID 0x0f34
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/* Serial IO 2 */
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#define SIO2_DEV 0x1e
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# define SIO_DMA2_DEV SIO2_DEV
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# define SIO_DMA2_FUNC 0
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# define SIO_DMA2_DEVID 0x0f06
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# define PWM1_DEV SIO2_DEV
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# define PWM1_FUNC 1
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# define PWM1_DEVID 0x0f08
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# define PWM2_DEV SIO2_DEV
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# define PWM2_FUNC 2
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# define PWM2_DEVID 0x0f09
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# define HSUART1_DEV SIO2_DEV
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# define HSUART1_FUNC 3
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# define HSUART1_DEVID 0x0f0a
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# define HSUART2_DEV SIO2_DEV
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# define HSUART2_FUNC 4
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# define HSUART2_DEVID 0x0f0c
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# define SPI_DEV SIO2_DEV
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# define SPI_FUNC 5
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# define SPI_DEVID 0xf0e
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/* Platform Controller Unit */
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#define PCU_DEV 0x1f
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# define LPC_DEV PCU_DEV
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# define LPC_FUNC 0
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# define LPC_DEVID 0x0f1c
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# define SMBUS_DEV PCU_DEV
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# define SMBUS_FUNC 3
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# define SMBUS_DEVID 0x0f12
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#define SOC_DEVID 0x0f00
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#define GFX_DEVID 0x0f31
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#define SDIO_DEVID 0x0f15
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#define SD_DEVID 0x0f16
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#define IDE1_DEVID 0x0f20
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#define IDE2_DEVID 0x0f21
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#define AHCI1_DEVID 0x0f22
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#define AHCI2_DEVID 0x0f23
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#define XHCI_DEVID 0x0f35
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#define LPE_DEVID 0x0f28
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#define MMC_DEVID 0x0f50
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#define SIO_DMA1_DEVID 0x0f40
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#define I2C1_DEVID 0x0f41
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#define I2C2_DEVID 0x0f42
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#define I2C3_DEVID 0x0f43
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#define I2C4_DEVID 0x0f44
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#define I2C5_DEVID 0x0f45
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#define I2C6_DEVID 0x0f46
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#define I2C7_DEVID 0x0f47
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#define TXE_DEVID 0x0f18
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#define HDA_DEVID 0x0f04
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#define PCIE_PORT1_DEVID 0x0f48
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#define PCIE_PORT2_DEVID 0x0f4a
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#define PCIE_PORT3_DEVID 0x0f4c
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#define PCIE_PORT4_DEVID 0x0f4e
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#define EHCI_DEVID 0x0f34
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#define SIO_DMA2_DEVID 0x0f06
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#define PWM1_DEVID 0x0f08
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#define PWM2_DEVID 0x0f09
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#define HSUART1_DEVID 0x0f0a
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#define HSUART2_DEVID 0x0f0c
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#define SPI_DEVID 0xf0e
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#define LPC_DEVID 0x0f1c
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#define SMBUS_DEVID 0x0f12
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#endif /* _BAYTRAIL_PCI_DEVS_H_ */
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@ -23,99 +23,76 @@
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/* SoC transaction router */
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#define SOC_DEV 0x0
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#define SOC_FUNC 0
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# define SOC_DEVID 0x2280
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/* Graphics and Display */
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#define GFX_DEV 0x2
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#define GFX_FUNC 0
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# define GFX_DEVID 0x22b1
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/* P-Unit DPTF */
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#define PUNIT_DEV 0xB
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#define PUNIT_FUNC 0
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#define PUNIT_DEVID 0x22DC
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/* MMC Port */
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#define MMC_DEV 0x10
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#define MMC_FUNC 0
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# define MMC_DEVID 0x2294
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/* SDIO Port */
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#define SDIO_DEV 0x11
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#define SDIO_FUNC 0
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# define SDIO_DEVID 0x2295
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/* SD Port */
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#define SD_DEV 0x12
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#define SD_FUNC 0
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# define SD_DEVID 0x2296
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/* SATA */
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#define SATA_DEV 0x13
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#define SATA_FUNC 0
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#define AHCI1_DEVID 0x22a3
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/* xHCI */
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#define XHCI_DEV 0x14
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#define XHCI_FUNC 0
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#define XHCI_DEVID 0x22b5
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/* LPE Audio */
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#define LPE_DEV 0x15
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#define LPE_FUNC 0
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# define LPE_DEVID 0x22a8
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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# define SIO_DMA1_DEV SIO1_DEV
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# define SIO_DMA1_FUNC 0
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# define SIO_DMA1_DEVID 0x22c0
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# define I2C1_DEV SIO1_DEV
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# define I2C1_FUNC 1
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# define I2C1_DEVID 0x22c1
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# define I2C2_DEV SIO1_DEV
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# define I2C2_FUNC 2
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# define I2C2_DEVID 0x22c2
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# define I2C3_DEV SIO1_DEV
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# define I2C3_FUNC 3
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# define I2C3_DEVID 0x22c3
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# define I2C4_DEV SIO1_DEV
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# define I2C4_FUNC 4
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# define I2C4_DEVID 0x22c4
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# define I2C5_DEV SIO1_DEV
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# define I2C5_FUNC 5
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# define I2C5_DEVID 0x22c5
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# define I2C6_DEV SIO1_DEV
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# define I2C6_FUNC 6
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# define I2C6_DEVID 0x22c6
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# define I2C7_DEV SIO1_DEV
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# define I2C7_FUNC 7
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# define I2C7_DEVID 0x22c7
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/* Trusted Execution Engine */
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#define TXE_DEV 0x1a
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#define TXE_FUNC 0
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# define TXE_DEVID 0x2298
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/* HD Audio */
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#define HDA_DEV 0x1b
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#define HDA_FUNC 0
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# define HDA_DEVID 0x2284
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/* PCIe Ports */
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#define PCIE_DEV 0x1c
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# define PCIE_PORT1_DEV PCIE_DEV
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# define PCIE_PORT1_FUNC 0
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# define PCIE_PORT1_DEVID 0x22c8
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# define PCIE_PORT2_DEV PCIE_DEV
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# define PCIE_PORT2_FUNC 1
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# define PCIE_PORT2_DEVID 0x22ca
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# define PCIE_PORT3_DEV PCIE_DEV
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# define PCIE_PORT3_FUNC 2
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# define PCIE_PORT3_DEVID 0x22cc
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# define PCIE_PORT4_DEV PCIE_DEV
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# define PCIE_PORT4_FUNC 3
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# define PCIE_PORT4_DEVID 0x22ce
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/* Total number of ROOT PORTS */
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#define MAX_ROOT_PORTS_BSW 4
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@ -123,34 +100,59 @@
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#define SIO2_DEV 0x1e
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# define SIO_DMA2_DEV SIO2_DEV
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# define SIO_DMA2_FUNC 0
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# define SIO_DMA2_DEVID 0x2286
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# define PWM1_DEV SIO2_DEV
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# define PWM1_FUNC 1
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# define PWM1_DEVID 0x2288
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# define PWM2_DEV SIO2_DEV
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# define PWM2_FUNC 2
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# define PWM2_DEVID 0x2289
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# define HSUART1_DEV SIO2_DEV
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# define HSUART1_FUNC 3
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# define HSUART1_DEVID 0x228a
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# define HSUART2_DEV SIO2_DEV
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# define HSUART2_FUNC 4
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# define HSUART2_DEVID 0x228c
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# define SPI_DEV SIO2_DEV
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# define SPI_FUNC 5
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# define SPI_DEVID 0x228e
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/* Platform Controller Unit */
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#define PCU_DEV 0x1f
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# define LPC_DEV PCU_DEV
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# define LPC_FUNC 0
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# define LPC_DEVID 0x229c
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# define SMBUS_DEV PCU_DEV
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# define SMBUS_FUNC 3
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# define SMBUS_DEVID 0x0f12
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/* PCH SCC Device Modes */
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#define PCH_DISABLED 0
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#define PCH_PCI_MODE 1
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#define PCH_ACPI_MODE 2
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#define SOC_DEVID 0x2280
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#define GFX_DEVID 0x22b1
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#define PUNIT_DEVID 0x22DC
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#define MMC_DEVID 0x2294
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#define SDIO_DEVID 0x2295
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#define SD_DEVID 0x2296
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#define AHCI1_DEVID 0x22a3
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#define XHCI_DEVID 0x22b5
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#define LPE_DEVID 0x22a8
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#define SIO_DMA1_DEVID 0x22c0
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#define I2C1_DEVID 0x22c1
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#define I2C2_DEVID 0x22c2
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#define I2C3_DEVID 0x22c3
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#define I2C4_DEVID 0x22c4
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#define I2C5_DEVID 0x22c5
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#define I2C6_DEVID 0x22c6
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#define I2C7_DEVID 0x22c7
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#define TXE_DEVID 0x2298
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#define HDA_DEVID 0x2284
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#define PCIE_PORT1_DEVID 0x22c8
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#define PCIE_PORT2_DEVID 0x22ca
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#define PCIE_PORT3_DEVID 0x22cc
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#define PCIE_PORT4_DEVID 0x22ce
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#define SIO_DMA2_DEVID 0x2286
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#define PWM1_DEVID 0x2288
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#define PWM2_DEVID 0x2289
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#define HSUART1_DEVID 0x228a
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#define HSUART2_DEVID 0x228c
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#define SPI_DEVID 0x228e
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#define LPC_DEVID 0x229c
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#define SMBUS_DEVID 0x0f12
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#endif /* _SOC_PCI_DEVS_H_ */
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@ -34,157 +34,116 @@
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/* SoC transaction router */
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#define SA_DEV 0x0
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#define SA_FUNC 0
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#define SA_DEVID 0x1980
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#define SA_DEVID_DNVAD 0x1995
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#define SOC_DEV SA_DEV
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#define SOC_FUNC SA_FUNC
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#define SOC_DEVID SA_DEVID
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/* RAS */
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#define RAS_DEV 0x4
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#define RAS_FUNC 0
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#define RAS_DEVID 0x19a1
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/* Root Complex Event Collector */
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#define RCEC_DEV 0x5
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#define RCEC_FUNC 0
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#define RCEC_DEVID 0x19a2
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/* Virtual Root Port 2 */
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#define VRP2_DEV 0x6
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#define VRP2_FUNC 0
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#define VRP2_DEVID 0x19a3
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/* PCIe Root Ports */
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#define PCIE_DEV 0x09
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#define MAX_PCIE_PORT 0x8
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#define PCIE_PORT1_DEV 0x09
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#define PCIE_PORT1_FUNC 0
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#define PCIE_PORT1_DEVID 0x19a4
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#define PCIE_PORT2_DEV 0x0a
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#define PCIE_PORT2_FUNC 0
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#define PCIE_PORT2_DEVID 0x19a5
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#define PCIE_PORT3_DEV 0x0b
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#define PCIE_PORT3_FUNC 0
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#define PCIE_PORT3_DEVID 0x19a6
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#define PCIE_PORT4_DEV 0x0c
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#define PCIE_PORT4_FUNC 0
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#define PCIE_PORT4_DEVID 0x19a7
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#define PCIE_PORT5_DEV 0x0e
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#define PCIE_PORT5_FUNC 0
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#define PCIE_PORT5_DEVID 0x19a8
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#define PCIE_PORT6_DEV 0x0f
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#define PCIE_PORT6_FUNC 0
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#define PCIE_PORT6_DEVID 0x19a9
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#define PCIE_PORT7_DEV 0x10
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#define PCIE_PORT7_FUNC 0
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#define PCIE_PORT7_DEVID 0x19aa
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#define PCIE_PORT8_DEV 0x11
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#define PCIE_PORT8_FUNC 0
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#define PCIE_PORT8_DEVID 0x19ab
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/* SMBUS 2 */
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#define SMBUS2_DEV 0x12
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#define SMBUS2_FUNC 0
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#define SMBUS2_DEVID 0x19ac
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/* SATA */
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#define SATA_DEV 0x13
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#define SATA_FUNC 0
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#define AHCI_DEVID 0x19b2
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#define SATA2_DEV 0x14
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#define SATA2_FUNC 0
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#define AHCI2_DEVID 0x19c2
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/* xHCI */
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#define XHCI_DEV 0x15
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#define XHCI_FUNC 0
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#define XHCI_DEVID 0x19d0
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/* Virtual Root Port 0 */
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#define VRP0_DEV 0x16
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#define VRP0_FUNC 0
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#define VRP0_DEVID 0x19d1
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/* Virtual Root Port 1 */
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#define VRP1_DEV 0x17
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#define VRP1_FUNC 0
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#define VRP1_DEVID 0x19d2
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/* CSME */
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#define ME_HECI_DEV 0x18
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#define ME_HECI1_DEV ME_HECI_DEV
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#define ME_HECI1_FUNC 0
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#define ME_HECI1_DEVID 0x19d3
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#define ME_HECI2_DEV ME_HECI_DEV
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#define ME_HECI2_FUNC 1
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#define ME_HECI2_DEVID 0x19d4
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#define ME_IEDR_DEV ME_HECI_DEV
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#define ME_IEDR_FUNC 2
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#define ME_IEDR_DEVID 0x19ea
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#define ME_MEKT_DEV ME_HECI_DEV
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#define ME_MEKT_FUNC 3
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#define ME_MEKT_DEVID 0x19d5
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#define ME_HECI3_DEV ME_HECI_DEV
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#define ME_HECI3_FUNC 4
|
||||
#define ME_HECI3_DEVID 0x19d6
|
||||
|
||||
/* HSUART */
|
||||
#define HSUART_DEV 0x1a
|
||||
#define HSUART_DEVID 0x19d8
|
||||
#define HSUART1_DEV HSUART_DEV
|
||||
#define HSUART1_FUNC 0
|
||||
#define HSUART1_DEVID HSUART_DEVID
|
||||
#define HSUART2_DEV HSUART_DEV
|
||||
#define HSUART2_FUNC 1
|
||||
#define HSUART2_DEVID HSUART_DEVID
|
||||
#define HSUART3_DEV HSUART_DEV
|
||||
#define HSUART3_FUNC 2
|
||||
#define HSUART3_DEVID HSUART_DEVID
|
||||
|
||||
/* IE */
|
||||
#define IE_HECI_DEV 0x1b
|
||||
#define IE_HECI1_DEV IE_HECI_DEV
|
||||
#define IE_HECI1_FUNC 0
|
||||
#define IE_HECI1_DEVID 0x19e5
|
||||
#define IE_HECI2_DEV IE_HECI_DEV
|
||||
#define IE_HECI2_FUNC 1
|
||||
#define IE_HECI2_DEVID 0x19e6
|
||||
#define IE_IEDR_DEV IE_HECI_DEV
|
||||
#define IE_IEDR_FUNC 2
|
||||
#define IE_IEDR_DEVID 0x19e7
|
||||
#define IE_MEKT_DEV IE_HECI_DEV
|
||||
#define IE_MEKT_FUNC 3
|
||||
#define IE_MEKT_DEVID 0x19e8
|
||||
#define IE_HECI3_DEV IE_HECI_DEV
|
||||
#define IE_HECI3_FUNC 4
|
||||
#define IE_HECI3_DEVID 0x19e9
|
||||
|
||||
/* MMC Port */
|
||||
#define MMC_DEV 0x1c
|
||||
#define MMC_FUNC 0
|
||||
#define MMC_DEVID 0x19db
|
||||
|
||||
/* Platform Controller Unit */
|
||||
#define PCU_DEV 0x1f
|
||||
#define LPC_DEV PCU_DEV
|
||||
#define LPC_FUNC 0
|
||||
#define LPC_DEVID 0x19dc
|
||||
#define P2SB_DEV PCU_DEV
|
||||
#define P2SB_FUNC 1
|
||||
#define P2SB_DEVID 0x19dd
|
||||
#define PMC_DEV PCU_DEV
|
||||
#define PMC_FUNC 2
|
||||
#define PMC_DEVID 0x19de
|
||||
#define SMBUS_DEV PCU_DEV
|
||||
#define SMBUS_FUNC 4
|
||||
#define SMBUS_DEVID 0x19df
|
||||
#define SPI_DEV PCU_DEV
|
||||
#define SPI_FUNC 5
|
||||
#define SPI_DEVID 0x19e0
|
||||
#define NPK_DEV PCU_DEV
|
||||
#define NPK_FUNC 7
|
||||
#define NPK_DEVID 0x19e1
|
||||
|
||||
/* TODO - New added */
|
||||
#define SA_DEV_SLOT_ROOT 0x00
|
||||
|
|
@ -199,4 +158,46 @@
|
|||
#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
|
||||
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
|
||||
|
||||
#define SA_DEVID 0x1980
|
||||
#define SA_DEVID_DNVAD 0x1995
|
||||
#define SOC_DEVID SA_DEVID
|
||||
#define RAS_DEVID 0x19a1
|
||||
#define RCEC_DEVID 0x19a2
|
||||
#define VRP2_DEVID 0x19a3
|
||||
#define PCIE_PORT1_DEVID 0x19a4
|
||||
#define PCIE_PORT2_DEVID 0x19a5
|
||||
#define PCIE_PORT3_DEVID 0x19a6
|
||||
#define PCIE_PORT4_DEVID 0x19a7
|
||||
#define PCIE_PORT5_DEVID 0x19a8
|
||||
#define PCIE_PORT6_DEVID 0x19a9
|
||||
#define PCIE_PORT7_DEVID 0x19aa
|
||||
#define PCIE_PORT8_DEVID 0x19ab
|
||||
#define SMBUS2_DEVID 0x19ac
|
||||
#define AHCI_DEVID 0x19b2
|
||||
#define AHCI2_DEVID 0x19c2
|
||||
#define XHCI_DEVID 0x19d0
|
||||
#define VRP0_DEVID 0x19d1
|
||||
#define VRP1_DEVID 0x19d2
|
||||
#define ME_HECI1_DEVID 0x19d3
|
||||
#define ME_HECI2_DEVID 0x19d4
|
||||
#define ME_IEDR_DEVID 0x19ea
|
||||
#define ME_MEKT_DEVID 0x19d5
|
||||
#define ME_HECI3_DEVID 0x19d6
|
||||
#define HSUART_DEVID 0x19d8
|
||||
#define HSUART1_DEVID HSUART_DEVID
|
||||
#define HSUART2_DEVID HSUART_DEVID
|
||||
#define HSUART3_DEVID HSUART_DEVID
|
||||
#define IE_HECI1_DEVID 0x19e5
|
||||
#define IE_HECI2_DEVID 0x19e6
|
||||
#define IE_IEDR_DEVID 0x19e7
|
||||
#define IE_MEKT_DEVID 0x19e8
|
||||
#define IE_HECI3_DEVID 0x19e9
|
||||
#define MMC_DEVID 0x19db
|
||||
#define LPC_DEVID 0x19dc
|
||||
#define P2SB_DEVID 0x19dd
|
||||
#define PMC_DEVID 0x19de
|
||||
#define SMBUS_DEVID 0x19df
|
||||
#define SPI_DEVID 0x19e0
|
||||
#define NPK_DEVID 0x19e1
|
||||
|
||||
#endif /* _DENVERTON_NS_PCI_DEVS_H_ */
|
||||
|
|
|
|||
|
|
@ -26,48 +26,38 @@
|
|||
/* SoC transaction router */
|
||||
#define SOC_DEV 0x0
|
||||
#define SOC_FUNC 0
|
||||
# define SOC_DEVID 0x0f00
|
||||
# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC)
|
||||
|
||||
|
||||
/* Graphics and Display */
|
||||
#define GFX_DEV 0x2
|
||||
#define GFX_FUNC 0
|
||||
# define GFX_DEVID 0x0f31
|
||||
# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC)
|
||||
|
||||
/* MIPI */
|
||||
#define MIPI_DEV 0x3
|
||||
#define MIPI_FUNC 0
|
||||
# define MIPI_DEVID 0x0f38
|
||||
# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC)
|
||||
|
||||
|
||||
/* SDIO Port */
|
||||
#define EMMC_DEV 0x10
|
||||
#define EMMC_FUNC 0
|
||||
# define EMMC_DEVID 0x0f14
|
||||
# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC)
|
||||
|
||||
/* SDIO Port */
|
||||
#define SDIO_DEV 0x11
|
||||
#define SDIO_FUNC 0
|
||||
# define SDIO_DEVID 0x0f15
|
||||
# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC)
|
||||
|
||||
/* SD Port */
|
||||
#define SD_DEV 0x12
|
||||
#define SD_FUNC 0
|
||||
# define SD_DEVID 0x0f16
|
||||
# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC)
|
||||
|
||||
/* SATA */
|
||||
#define SATA_DEV 0x13
|
||||
#define SATA_FUNC 0
|
||||
# define IDE1_DEVID 0x0f20
|
||||
# define IDE2_DEVID 0x0f21
|
||||
# define AHCI1_DEVID 0x0f22
|
||||
# define AHCI2_DEVID 0x0f23
|
||||
# define SATA_MA 0x84
|
||||
# define SATA_MAP 0x90
|
||||
# define SATA_PSC 0x92
|
||||
|
|
@ -84,7 +74,6 @@
|
|||
/* xHCI */
|
||||
#define XHCI_DEV 0x14
|
||||
#define XHCI_FUNC 0
|
||||
# define XHCI_DEVID 0x0f35
|
||||
# define XHCI_FUS_REG 0xE0
|
||||
# define XHCI_FUNC_DISABLE (1 << 0)
|
||||
# define XHCI_USB2PR_REG 0xD0
|
||||
|
|
@ -93,47 +82,36 @@
|
|||
/* LPE Audio */
|
||||
#define LPE_DEV 0x15
|
||||
#define LPE_FUNC 0
|
||||
# define LPE_DEVID 0x0f28
|
||||
# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC)
|
||||
|
||||
/* OTG */
|
||||
#define OTG_DEV 0x16
|
||||
#define OTG_FUNC 0
|
||||
# define OTG_DEVID 0x0f37
|
||||
# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC)
|
||||
|
||||
/* MMC Port */
|
||||
#define MMC45_DEV 0x17
|
||||
#define MMC45_FUNC 0
|
||||
# define MMC45_DEVID 0x0f50
|
||||
# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC)
|
||||
|
||||
/* Serial IO 1 */
|
||||
#define SIO1_DEV 0x18
|
||||
# define SIO_DMA1_DEV SIO1_DEV
|
||||
# define SIO_DMA1_FUNC 0
|
||||
# define SIO_DMA1_DEVID 0x0f40
|
||||
# define I2C1_DEV SIO1_DEV
|
||||
# define I2C1_FUNC 1
|
||||
# define I2C1_DEVID 0x0f41
|
||||
# define I2C2_DEV SIO1_DEV
|
||||
# define I2C2_FUNC 2
|
||||
# define I2C2_DEVID 0x0f42
|
||||
# define I2C3_DEV SIO1_DEV
|
||||
# define I2C3_FUNC 3
|
||||
# define I2C3_DEVID 0x0f43
|
||||
# define I2C4_DEV SIO1_DEV
|
||||
# define I2C4_FUNC 4
|
||||
# define I2C4_DEVID 0x0f44
|
||||
# define I2C5_DEV SIO1_DEV
|
||||
# define I2C5_FUNC 5
|
||||
# define I2C5_DEVID 0x0f45
|
||||
# define I2C6_DEV SIO1_DEV
|
||||
# define I2C6_FUNC 6
|
||||
# define I2C6_DEVID 0x0f46
|
||||
# define I2C7_DEV SIO1_DEV
|
||||
# define I2C7_FUNC 7
|
||||
# define I2C7_DEVID 0x0f47
|
||||
# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC)
|
||||
# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC)
|
||||
# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC)
|
||||
|
|
@ -146,13 +124,11 @@
|
|||
/* Trusted Execution Engine */
|
||||
#define TXE_DEV 0x1a
|
||||
#define TXE_FUNC 0
|
||||
# define TXE_DEVID 0x0f18
|
||||
# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC)
|
||||
|
||||
/* HD Audio */
|
||||
#define HDA_DEV 0x1b
|
||||
#define HDA_FUNC 0
|
||||
# define HDA_DEVID 0x0f04
|
||||
# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC)
|
||||
# define HDA_AZUBAR 0x14
|
||||
# define HDA_MMLA 0x64
|
||||
|
|
@ -165,16 +141,12 @@
|
|||
#define PCIE_DEV 0x1c
|
||||
# define PCIE_PORT1_DEV PCIE_DEV
|
||||
# define PCIE_PORT1_FUNC 0
|
||||
# define PCIE_PORT1_DEVID 0x0f48
|
||||
# define PCIE_PORT2_DEV PCIE_DEV
|
||||
# define PCIE_PORT2_FUNC 1
|
||||
# define PCIE_PORT2_DEVID 0x0f4a
|
||||
# define PCIE_PORT3_DEV PCIE_DEV
|
||||
# define PCIE_PORT3_FUNC 2
|
||||
# define PCIE_PORT3_DEVID 0x0f4c
|
||||
# define PCIE_PORT4_DEV PCIE_DEV
|
||||
# define PCIE_PORT4_FUNC 3
|
||||
# define PCIE_PORT4_DEVID 0x0f4e
|
||||
# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC)
|
||||
# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC)
|
||||
# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC)
|
||||
|
|
@ -183,29 +155,22 @@
|
|||
/* EHCI */
|
||||
#define EHCI_DEV 0x1d
|
||||
#define EHCI_FUNC 0
|
||||
# define EHCI_DEVID 0x0f34
|
||||
# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC)
|
||||
|
||||
/* Serial IO 2 */
|
||||
#define SIO2_DEV 0x1e
|
||||
# define SIO_DMA2_DEV SIO2_DEV
|
||||
# define SIO_DMA2_FUNC 0
|
||||
# define SIO_DMA2_DEVID 0x0f06
|
||||
# define PWM1_DEV SIO2_DEV
|
||||
# define PWM1_FUNC 1
|
||||
# define PWM1_DEVID 0x0f08
|
||||
# define PWM2_DEV SIO2_DEV
|
||||
# define PWM2_FUNC 2
|
||||
# define PWM2_DEVID 0x0f09
|
||||
# define HSUART1_DEV SIO2_DEV
|
||||
# define HSUART1_FUNC 3
|
||||
# define HSUART1_DEVID 0x0f0a
|
||||
# define HSUART2_DEV SIO2_DEV
|
||||
# define HSUART2_FUNC 4
|
||||
# define HSUART2_DEVID 0x0f0c
|
||||
# define SPI_DEV SIO2_DEV
|
||||
# define SPI_FUNC 5
|
||||
# define SPI_DEVID 0xf0e
|
||||
# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC)
|
||||
# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC)
|
||||
# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC)
|
||||
|
|
@ -218,10 +183,8 @@
|
|||
#define PCU_DEV 0x1f
|
||||
# define LPC_DEV PCU_DEV
|
||||
# define LPC_FUNC 0
|
||||
# define LPC_DEVID 0x0f1c
|
||||
# define SMBUS_DEV PCU_DEV
|
||||
# define SMBUS_FUNC 3
|
||||
# define SMBUS_DEVID 0x0f12
|
||||
# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC)
|
||||
# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC)
|
||||
# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
|
||||
|
|
@ -234,4 +197,43 @@
|
|||
#define START_ROMSTAGE_TIMESTAMP_LOCATION HDA_MMLA_BDFO
|
||||
#define BEFORE_RAMINIT_TIMESTAMP_LOCATION SATA_MA_BDFO
|
||||
|
||||
|
||||
#define SOC_DEVID 0x0f00
|
||||
#define GFX_DEVID 0x0f31
|
||||
#define MIPI_DEVID 0x0f38
|
||||
#define EMMC_DEVID 0x0f14
|
||||
#define SDIO_DEVID 0x0f15
|
||||
#define SD_DEVID 0x0f16
|
||||
#define IDE1_DEVID 0x0f20
|
||||
#define IDE2_DEVID 0x0f21
|
||||
#define AHCI1_DEVID 0x0f22
|
||||
#define AHCI2_DEVID 0x0f23
|
||||
#define XHCI_DEVID 0x0f35
|
||||
#define LPE_DEVID 0x0f28
|
||||
#define OTG_DEVID 0x0f37
|
||||
#define MMC45_DEVID 0x0f50
|
||||
#define SIO_DMA1_DEVID 0x0f40
|
||||
#define I2C1_DEVID 0x0f41
|
||||
#define I2C2_DEVID 0x0f42
|
||||
#define I2C3_DEVID 0x0f43
|
||||
#define I2C4_DEVID 0x0f44
|
||||
#define I2C5_DEVID 0x0f45
|
||||
#define I2C6_DEVID 0x0f46
|
||||
#define I2C7_DEVID 0x0f47
|
||||
#define TXE_DEVID 0x0f18
|
||||
#define HDA_DEVID 0x0f04
|
||||
#define PCIE_PORT1_DEVID 0x0f48
|
||||
#define PCIE_PORT2_DEVID 0x0f4a
|
||||
#define PCIE_PORT3_DEVID 0x0f4c
|
||||
#define PCIE_PORT4_DEVID 0x0f4e
|
||||
#define EHCI_DEVID 0x0f34
|
||||
#define SIO_DMA2_DEVID 0x0f06
|
||||
#define PWM1_DEVID 0x0f08
|
||||
#define PWM2_DEVID 0x0f09
|
||||
#define HSUART1_DEVID 0x0f0a
|
||||
#define HSUART2_DEVID 0x0f0c
|
||||
#define SPI_DEVID 0xf0e
|
||||
#define LPC_DEVID 0x0f1c
|
||||
#define SMBUS_DEVID 0x0f12
|
||||
|
||||
#endif /* _BAYTRAIL_PCI_DEVS_H_ */
|
||||
|
|
|
|||
|
|
@ -24,8 +24,6 @@
|
|||
|
||||
#define SOC_DEV 0
|
||||
#define SOC_FUNC 0
|
||||
#define SOC_DEVID 0x2F00
|
||||
#define SOC_DEVID_ES2 0x6F00
|
||||
#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC)
|
||||
|
||||
/* DMI2/PCIe link to PCH */
|
||||
|
|
@ -53,24 +51,19 @@
|
|||
|
||||
#define VTD_DEV 5
|
||||
#define VTD_FUNC 0
|
||||
#define VTD_DEVID 0x6f28
|
||||
#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC)
|
||||
#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC)
|
||||
|
||||
#define LPC_DEV 31
|
||||
#define LPC_FUNC 0
|
||||
#define LPC_DEVID 0x8C42
|
||||
#define LPC_DEVID_ES2 0x8C54
|
||||
#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC)
|
||||
|
||||
#define SATA_DEV 31
|
||||
#define SATA_FUNC 2
|
||||
#define AHCI_DEVID 0x8C02
|
||||
#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC)
|
||||
|
||||
#define SMBUS_DEV 31
|
||||
#define SMBUS_FUNC 3
|
||||
#define SMBUS_DEVID 0x8C22
|
||||
#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
|
||||
|
||||
#define SATA2_DEV 31
|
||||
|
|
@ -79,17 +72,14 @@
|
|||
|
||||
#define EHCI1_DEV 29
|
||||
#define EHCI1_FUNC 0
|
||||
#define EHCI1_DEVID 0x8C26
|
||||
#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1)
|
||||
|
||||
#define EHCI2_DEV 26
|
||||
#define EHCI2_FUNC 0
|
||||
#define EHCI2_DEVID 0x8C2D
|
||||
#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2)
|
||||
|
||||
#define XHCI_DEV 20
|
||||
#define XHCI_FUNC 0
|
||||
#define XHCI_DEVID 0x8C31
|
||||
#define XHCI_FUS_REG 0xE0
|
||||
#define XHCI_FUNC_DISABLE (1 << 0)
|
||||
#define XHCI_USB2PR_REG 0xD0
|
||||
|
|
@ -97,45 +87,34 @@
|
|||
|
||||
#define GBE_DEV 25
|
||||
#define GBE_FUNC 0
|
||||
#define GBE_DEVID 0x8C33
|
||||
#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC)
|
||||
|
||||
#define ME_DEV 22
|
||||
#define ME_FUNC 0
|
||||
#define ME_DEVID 0x8C3A
|
||||
#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC)
|
||||
|
||||
#define HDA_DEV 27
|
||||
#define HDA_FUNC 0
|
||||
#define HDA_DEVID 0x8C20
|
||||
#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC)
|
||||
|
||||
/* Ports from PCH block with adjustable burification settings */
|
||||
#define PCIE_DEV 28
|
||||
#define PCIE_PORT1_DEV PCIE_DEV
|
||||
#define PCIE_PORT1_FUNC 0
|
||||
#define PCIE_PORT1_DEVID 0x8C10
|
||||
#define PCIE_PORT2_DEV PCIE_DEV
|
||||
#define PCIE_PORT2_FUNC 1
|
||||
#define PCIE_PORT2_DEVID 0x8C12
|
||||
#define PCIE_PORT3_DEV PCIE_DEV
|
||||
#define PCIE_PORT3_FUNC 2
|
||||
#define PCIE_PORT3_DEVID 0x8C14
|
||||
#define PCIE_PORT4_DEV PCIE_DEV
|
||||
#define PCIE_PORT4_FUNC 3
|
||||
#define PCIE_PORT4_DEVID 0x8C16
|
||||
#define PCIE_PORT5_DEV PCIE_DEV
|
||||
#define PCIE_PORT5_FUNC 4
|
||||
#define PCIE_PORT5_DEVID 0x8C18
|
||||
#define PCIE_PORT6_DEV PCIE_DEV
|
||||
#define PCIE_PORT6_FUNC 5
|
||||
#define PCIE_PORT6_DEVID 0x8C1A
|
||||
#define PCIE_PORT7_DEV PCIE_DEV
|
||||
#define PCIE_PORT7_FUNC 6
|
||||
#define PCIE_PORT7_DEVID 0x8C1C
|
||||
#define PCIE_PORT8_DEV PCIE_DEV
|
||||
#define PCIE_PORT8_FUNC 7
|
||||
#define PCIE_PORT8_DEVID 0x8C1E
|
||||
#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC)
|
||||
#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC)
|
||||
#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC)
|
||||
|
|
@ -161,4 +140,27 @@
|
|||
#define UBOX_DEV 16
|
||||
#define UBOX_FUNC 7
|
||||
|
||||
|
||||
#define SOC_DEVID 0x2F00
|
||||
#define SOC_DEVID_ES2 0x6F00
|
||||
#define VTD_DEVID 0x6f28
|
||||
#define LPC_DEVID 0x8C42
|
||||
#define LPC_DEVID_ES2 0x8C54
|
||||
#define AHCI_DEVID 0x8C02
|
||||
#define SMBUS_DEVID 0x8C22
|
||||
#define EHCI1_DEVID 0x8C26
|
||||
#define EHCI2_DEVID 0x8C2D
|
||||
#define XHCI_DEVID 0x8C31
|
||||
#define GBE_DEVID 0x8C33
|
||||
#define ME_DEVID 0x8C3A
|
||||
#define HDA_DEVID 0x8C20
|
||||
#define PCIE_PORT1_DEVID 0x8C10
|
||||
#define PCIE_PORT2_DEVID 0x8C12
|
||||
#define PCIE_PORT3_DEVID 0x8C14
|
||||
#define PCIE_PORT4_DEVID 0x8C16
|
||||
#define PCIE_PORT5_DEVID 0x8C18
|
||||
#define PCIE_PORT6_DEVID 0x8C1A
|
||||
#define PCIE_PORT7_DEVID 0x8C1C
|
||||
#define PCIE_PORT8_DEVID 0x8C1E
|
||||
|
||||
#endif /* _SOC_PCI_DEVS_H_ */
|
||||
|
|
|
|||
|
|
@ -26,87 +26,71 @@
|
|||
/* Host Bridge */
|
||||
#define SOC_DEV 0x0
|
||||
#define SOC_FUNC 0
|
||||
# define SOC_DEVID 0x1f08
|
||||
# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC)
|
||||
|
||||
/* PCIE Port 1 */
|
||||
#define PCIE_PORT1_DEV 0x1
|
||||
#define PCIE_PORT1_FUNC 0
|
||||
# define PCIE_PORT1_DEVID 0x1f10
|
||||
# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
|
||||
|
||||
/* PCIE Port 2 */
|
||||
#define PCIE_PORT2_DEV 0x2
|
||||
#define PCIE_PORT2_FUNC 0
|
||||
# define PCIE_PORT2_DEVID 0x1f11
|
||||
# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
|
||||
|
||||
/* PCIE Port 3 */
|
||||
#define PCIE_PORT3_DEV 0x3
|
||||
#define PCIE_PORT3_FUNC 0
|
||||
# define PCIE_PORT3_DEVID 0x1f12
|
||||
# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
|
||||
|
||||
/* PCIE Port 4 */
|
||||
#define PCIE_PORT4_DEV 0x4
|
||||
#define PCIE_PORT4_FUNC 0
|
||||
# define PCIE_PORT4_DEVID 0x1f13
|
||||
# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
|
||||
|
||||
/* Host Bridge, Fabric, and RAS Registers */
|
||||
#define HOST_BRIDGE_DEV 0xe
|
||||
#define HOST_BRIDGE_FUNC 0
|
||||
# define HOST_BRIDGE_DEVID 0x1f14
|
||||
# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
|
||||
|
||||
/* Root Complex Event Collector (RCEC) */
|
||||
#define RCEC_DEV 0xf
|
||||
#define RCEC_FUNC 0
|
||||
# define RCEC_DEVID 0x1f16
|
||||
# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
|
||||
|
||||
/* SMBus 2.0 1 */
|
||||
#define SMBUS1_DEV 0x13
|
||||
#define SMBUS1_FUNC 0
|
||||
# define SMBUS1_DEVID 0x1f15
|
||||
# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
|
||||
|
||||
/* Gigabit Ethernet (GbE) */
|
||||
#define GBE_DEV 0x14
|
||||
#define GBE_DEVID 0x1f41
|
||||
#define GBE1_DEV GBE_DEV
|
||||
#define GBE1_FUNC 0
|
||||
# define GBE1_DEVID GBE_DEVID
|
||||
# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
|
||||
#define GBE2_DEV GBE_DEV
|
||||
#define GBE2_FUNC 1
|
||||
# define GBE2_DEVID GBE_DEVID
|
||||
# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
|
||||
#define GBE3_DEV GBE_DEV
|
||||
#define GBE3_FUNC 2
|
||||
# define GBE3_DEVID GBE_DEVID
|
||||
# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
|
||||
#define GBE4_DEV GBE_DEV
|
||||
#define GBE4_FUNC 3
|
||||
# define GBE4_DEVID GBE_DEVID
|
||||
# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
|
||||
|
||||
/* USB 2.0 */
|
||||
#define USB2_DEV 0x16
|
||||
#define USB2_FUNC 0
|
||||
# define USB2_DEVID 0x1f2c
|
||||
# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC)
|
||||
|
||||
/* SATA Gen 2 */
|
||||
#define SATA2_DEV 0x17
|
||||
#define SATA2_FUNC 0
|
||||
# define SATA2_DEVID 0x1f22
|
||||
# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
|
||||
|
||||
/* SATA Gen 3 */
|
||||
#define SATA3_DEV 0x18
|
||||
#define SATA3_FUNC 0
|
||||
# define SATA3_DEVID 0x1f32
|
||||
# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
|
||||
|
||||
/* Platform Control Unit (PCU) */
|
||||
|
|
@ -115,20 +99,37 @@
|
|||
/* Low Pin Count (LPC/ISA) */
|
||||
#define LPC_DEV PCU_DEV
|
||||
#define LPC_FUNC 0
|
||||
# define LPC_DEVID 0x1f38
|
||||
# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC)
|
||||
# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
|
||||
|
||||
/* SMBus 2.0 0 */
|
||||
#define SMBUS0_DEV PCU_DEV
|
||||
#define SMBUS0_FUNC 3
|
||||
# define SMBUS0_DEVID 0x1f3c
|
||||
# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
|
||||
|
||||
/* Intel QuickAssist Integrated Accelerator (IQIA) */
|
||||
#define IQAT_DEV 0xb
|
||||
#define IQAT_FUNC 0
|
||||
# define IQAT_DEVID 0x1f18
|
||||
# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
|
||||
|
||||
#define SOC_DEVID 0x1f08
|
||||
#define PCIE_PORT1_DEVID 0x1f10
|
||||
#define PCIE_PORT2_DEVID 0x1f11
|
||||
#define PCIE_PORT3_DEVID 0x1f12
|
||||
#define PCIE_PORT4_DEVID 0x1f13
|
||||
#define HOST_BRIDGE_DEVID 0x1f14
|
||||
#define RCEC_DEVID 0x1f16
|
||||
#define SMBUS1_DEVID 0x1f15
|
||||
#define GBE_DEVID 0x1f41
|
||||
#define GBE1_DEVID GBE_DEVID
|
||||
#define GBE2_DEVID GBE_DEVID
|
||||
#define GBE3_DEVID GBE_DEVID
|
||||
#define GBE4_DEVID GBE_DEVID
|
||||
#define USB2_DEVID 0x1f2c
|
||||
#define SATA2_DEVID 0x1f22
|
||||
#define SATA3_DEVID 0x1f32
|
||||
#define LPC_DEVID 0x1f38
|
||||
#define SMBUS0_DEVID 0x1f3c
|
||||
#define IQAT_DEVID 0x1f18
|
||||
|
||||
#endif /* _RANGELEY_PCI_DEVS_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue