amd/stoneyridge: Relocate MCA error identification

Move the process of interrogating the Machine Check registers into
its own file.  This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/amd/stoneyridge/Makefile.inc

@@ -92,6 +92,7 @@ ramstage-y += BiosCallOuts.c
 ramstage-y += i2c.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
+ramstage-y += mca.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += gpio.c

src/soc/amd/stoneyridge/cpu.c

@@ -117,62 +117,6 @@ void stoney_init_cpus(struct device *dev)
 	set_warm_reset_flag();
 }
 
-static const char *const mca_bank_name[] = {
-	"Load-store unit",
-	"Instruction fetch unit",
-	"Combined unit",
-	"Reserved",
-	"Northbridge",
-	"Execution unit",
-	"Floating point unit"
-};
-
-static void check_mca(void)
-{
-	int i;
-	msr_t msr;
-	int num_banks;
-
-	msr = rdmsr(MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-
-	if (is_warm_reset()) {
-		for (i = 0 ; i < num_banks ; i++) {
-			if (i == 3) /* Reserved in Family 15h */
-				continue;
-
-			msr = rdmsr(MC0_STATUS + (i * 4));
-			if (msr.hi || msr.lo) {
-				int core = cpuid_ebx(1) >> 24;
-
-				printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",
-						core, i, mca_bank_name[i]);
-
-				printk(BIOS_WARNING, "   MC%d_STATUS =   %08x_%08x\n",
-						i, msr.hi, msr.lo);
-				msr = rdmsr(MC0_ADDR + (i * 4));
-				printk(BIOS_WARNING, "   MC%d_ADDR =     %08x_%08x\n",
-						i, msr.hi, msr.lo);
-				msr = rdmsr(MC0_MISC + (i * 4));
-				printk(BIOS_WARNING, "   MC%d_MISC =     %08x_%08x\n",
-						i, msr.hi, msr.lo);
-				msr = rdmsr(MC0_CTL + (i * 4));
-				printk(BIOS_WARNING, "   MC%d_CTL =      %08x_%08x\n",
-						i, msr.hi, msr.lo);
-				msr = rdmsr(MC0_CTL_MASK + i);
-				printk(BIOS_WARNING, "   MC%d_CTL_MASK = %08x_%08x\n",
-						i, msr.hi, msr.lo);
-			}
-		}
-	}
-
-	/* zero the machine check error status registers */
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0 ; i < num_banks ; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
-}
-
 static void model_15_init(struct device *dev)
 {
 	check_mca();

src/soc/amd/stoneyridge/include/soc/cpu.h

@@ -30,5 +30,6 @@
 #define SOC_EARLY_VMTRR_TEMPRAM 3
 
 void stoney_init_cpus(struct device *dev);
+void check_mca(void);
 
 #endif /* __STONEYRIDGE_CPU_H__ */

src/soc/amd/stoneyridge/mca.c

@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/msr.h>
+#include <arch/acpi.h>
+#include <cpu/amd/amdfam15.h>
+#include <soc/cpu.h>
+#include <soc/northbridge.h>
+#include <console/console.h>
+
+static const char *const mca_bank_name[] = {
+	"Load-store unit",
+	"Instruction fetch unit",
+	"Combined unit",
+	"Reserved",
+	"Northbridge",
+	"Execution unit",
+	"Floating point unit"
+};
+
+void check_mca(void)
+{
+	int i;
+	msr_t msr;
+	int num_banks;
+
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
+
+	if (is_warm_reset()) {
+		for (i = 0 ; i < num_banks ; i++) {
+			if (i == 3) /* Reserved in Family 15h */
+				continue;
+
+			msr = rdmsr(MC0_STATUS + (i * 4));
+			if (msr.hi || msr.lo) {
+				int core = cpuid_ebx(1) >> 24;
+
+				printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",
+						core, i, mca_bank_name[i]);
+
+				printk(BIOS_WARNING, "   MC%d_STATUS =   %08x_%08x\n",
+						i, msr.hi, msr.lo);
+				msr = rdmsr(MC0_ADDR + (i * 4));
+				printk(BIOS_WARNING, "   MC%d_ADDR =     %08x_%08x\n",
+						i, msr.hi, msr.lo);
+				msr = rdmsr(MC0_MISC + (i * 4));
+				printk(BIOS_WARNING, "   MC%d_MISC =     %08x_%08x\n",
+						i, msr.hi, msr.lo);
+				msr = rdmsr(MC0_CTL + (i * 4));
+				printk(BIOS_WARNING, "   MC%d_CTL =      %08x_%08x\n",
+						i, msr.hi, msr.lo);
+				msr = rdmsr(MC0_CTL_MASK + i);
+				printk(BIOS_WARNING, "   MC%d_CTL_MASK = %08x_%08x\n",
+						i, msr.hi, msr.lo);
+			}
+		}
+	}
+
+	/* zero the machine check error status registers */
+	msr.lo = 0;
+	msr.hi = 0;
+	for (i = 0 ; i < num_banks ; i++)
+		wrmsr(MC0_STATUS + (i * 4), msr);
+}