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bayleybay_fsp: Switch from EHCI controller to XHCI 

- Disable the EHCI controller and enable the XHCI controller.

SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port.  The HSIC port is only enabled
through the XHCI device.

Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6106
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Martin Roth 2014-06-25 10:13:22 -06:00 committed by Martin Roth
parent e3c65b97b4
commit 0b4b230163
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/bayleybay_fsp/devicetree.cb
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@ -50,7 +50,7 @@ chip soc/intel/fsp_baytrail
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
@ -68,7 +68,7 @@ chip soc/intel/fsp_baytrail
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
device pci 1e.1 on end # 8086 0F08 - PWM 1
device pci 1e.2 on end # 8086 0F09 - PWM 2