soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register
Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Add a helper macro to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -145,6 +145,19 @@
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.pad_config[1] = __config1, \
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}
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#if GPIO_NUM_PAD_CFG_REGS > 2
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#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
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{ \
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.pad = __pad, \
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.pad_config[0] = __config0, \
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.pad_config[1] = __config1, \
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.pad_config[2] = __config2, \
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}
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#else
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#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
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_PAD_CFG_STRUCT(__pad, __config0, __config1)
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#endif
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/* Native function configuration */
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#define PAD_CFG_NF(pad, pull, rst, func) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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