mb/prodrive/hermes: Clean up some cosmetics
Use lowercase for hex numbers, sort includes alphabetically and avoid relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up the indentation of some includes. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -7,22 +7,19 @@ DefinitionBlock(
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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Scope (\_SB) {
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Device (PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -1,10 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <device/pci_ops.h>
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#include <delay.h>
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#include <console/console.h>
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#include <crc_byte.h>
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#include <delay.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <soc/intel/common/block/smbus/smbuslib.h>
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#include <types.h>
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@ -1,6 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <assert.h>
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#include <soc/ramstage.h>
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#include <types.h>
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union eeprom_dimm_layout {
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struct __packed {
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@ -71,7 +73,7 @@ struct __packed eeprom_layout {
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FSPM_UPD mupd;
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};
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union {
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uint8_t RawFSPSUPD[0xC00];
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uint8_t RawFSPSUPD[0xc00];
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FSPS_UPD supd;
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};
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union {
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@ -82,7 +84,7 @@ struct __packed eeprom_layout {
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char board_serial_number[HERMES_SERIAL_NUMBER_LENGTH];
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uint8_t BootOrder[0x8c0];
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union {
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uint8_t RawBoardSetting[0xF8];
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uint8_t RawBoardSetting[0xf8];
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struct eeprom_board_settings BoardSettings;
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};
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union {
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@ -92,7 +94,7 @@ struct __packed eeprom_layout {
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};
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_Static_assert(sizeof(FSPM_UPD) <= 0x600, "FSPM_UPD too big");
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_Static_assert(sizeof(FSPS_UPD) <= 0xC00, "FSPS_UPD too big");
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_Static_assert(sizeof(FSPS_UPD) <= 0xc00, "FSPS_UPD too big");
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_Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size mismatch");
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bool eeprom_read_buffer(void *blob, size_t read_offset, size_t size);
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@ -1,8 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/helpers.h>
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#include <intelblocks/gpio.h>
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#include <soc/gpio.h>
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#include <intelblocks/gpio_defs.h>
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#include "gpio.h"
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@ -21,7 +21,7 @@ const u32 cim_verb_data[] = {
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AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */
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AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */
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AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */
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AZALIA_PIN_CFG(0, 0x1f, 0x01C52170), /* SPDIF-IN */
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AZALIA_PIN_CFG(0, 0x1f, 0x01c52170), /* SPDIF-IN */
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/* Config for R02 and older */
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AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */
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@ -31,11 +31,11 @@ const u32 cim_verb_data[] = {
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/*
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* VerbTable: CFL Display Audio Codec
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* Revision ID = 0xFF
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* Codec Vendor: 0x8086280B
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* Revision ID = 0xff
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* Codec Vendor: 0x8086280b
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*/
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0x8086280B,
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0xFFFFFFFF,
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0x8086280b,
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0xffffffff,
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5, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(2, 0x80860101),
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@ -1,19 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cpu.h>
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#include <acpi/acpigen.h>
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#include <arch/cpu.h>
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <crc_byte.h>
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#include <bootstate.h>
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#include <device/device.h>
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#include <device/dram/spd.h>
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#include <gpio.h>
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#include <intelblocks/gpio_defs.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/pmclib.h>
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#include <smbios.h>
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#include <soc/gpio.h>
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#include <types.h>
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#include <smbios.h>
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#include "eeprom.h"
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#include "gpio.h"
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@ -9,19 +9,19 @@ static const struct cnl_mb_cfg baseboard_mem_cfg = {
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/* Access memory info through SMBUS. */
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.spd[0] = {
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.read_type = READ_SMBUS,
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.spd_spec = {.spd_smbus_address = 0xA0}
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.spd_spec = {.spd_smbus_address = 0xa0}
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},
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.spd[1] = {
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.read_type = READ_SMBUS,
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.spd_spec = {.spd_smbus_address = 0xA2}
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.spd_spec = {.spd_smbus_address = 0xa2}
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},
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.spd[2] = {
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.read_type = READ_SMBUS,
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.spd_spec = {.spd_smbus_address = 0xA4}
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.spd_spec = {.spd_smbus_address = 0xa4}
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},
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.spd[3] = {
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.read_type = READ_SMBUS,
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.spd_spec = {.spd_smbus_address = 0xA6}
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.spd_spec = {.spd_smbus_address = 0xa6}
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},
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/* Baseboard uses 121, 81 and 100 rcomp resistors */
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@ -1,8 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <smbios.h>
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#include <types.h>
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#include <string.h>
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#include <types.h>
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#include "eeprom.h"
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