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sb/intel/i82801gx,ix: Drop MPEN from GNVS 

It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-01-27 20:25:51 +02:00 committed by Patrick Georgi
parent da321d8834
commit 0b7446a269
8 changed files with 9 additions and 20 deletions
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4
src/cpu/intel/speedstep/acpi.c
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@ -133,4 +133,8 @@ void generate_cpu_entries(const struct device *device)
acpigen_write_processor_package("PPKG", 0, cores_per_package); acpigen_write_processor_package("PPKG", 0, cores_per_package);
acpigen_write_processor_cnot(cores_per_package); acpigen_write_processor_cnot(cores_per_package);
acpigen_write_scope("\\");
acpigen_write_name_integer("MPEN", numcpus > 1);
acpigen_pop_len();
} }

1
src/cpu/intel/speedstep/acpi/cpu.asl
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@ -5,6 +5,7 @@ External (\_SB.CNOT, MethodObj)
External (\_SB_.CP00, DeviceObj) External (\_SB_.CP00, DeviceObj)
External (\_SB_.CP00._PPC) External (\_SB_.CP00._PPC)
External (\_SB_.CP01._PPC) External (\_SB_.CP01._PPC)
External (\MPEN, IntObj)
Method (PNOT) Method (PNOT)
{ {

2
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
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@ -45,7 +45,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
, 8, // 0x28 - Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

2
src/southbridge/intel/i82801gx/include/soc/nvs.h
View File

@ -41,7 +41,7 @@ struct __packed global_nvs {
u8 rsvd3[3]; u8 rsvd3[3];
/* Processor Identification */ /* Processor Identification */
u8 unused_was_apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

8
src/southbridge/intel/i82801gx/lpc.c
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@ -12,7 +12,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
@ -21,7 +20,6 @@
#include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/hpet.h>
#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/spi.h> #include <southbridge/intel/common/spi.h>
#include <soc/nvs.h>
#include "chip.h" #include "chip.h"
#include "i82801gx.h" #include "i82801gx.h"
@ -464,12 +462,6 @@ static void lpc_final(struct device *dev)
outb(POST_OS_BOOT, 0x80); outb(POST_OS_BOOT, 0x80);
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* MPEN, Enable Multi Processing. */
gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";

2
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -46,7 +46,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
, 8, // 0x28 - Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

2
src/southbridge/intel/i82801ix/include/soc/nvs.h
View File

@ -41,7 +41,7 @@ struct __packed global_nvs {
u8 rsvd3[3]; u8 rsvd3[3];
/* Processor Identification */ /* Processor Identification */
u8 unused_was_apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

8
src/southbridge/intel/i82801ix/lpc.c
View File

@ -12,7 +12,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <string.h> #include <string.h>
@ -21,7 +20,6 @@
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <soc/nvs.h>
#define NMI_OFF 0 #define NMI_OFF 0
@ -452,12 +450,6 @@ static void i82801ix_lpc_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* MPEN, Enable Multi Processing. */
gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";