mb/amd/birman: add Phoenix with openSIL mainboard option
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL based Phoenix SoC code. Since the Phoenix chip.c is different due to some FSP-specific data structures in there that are guarded in the openSIL case, a separate devicetree for the openSIL case is added. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Felix Held
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09ea3499e7
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@ -19,6 +19,10 @@ config BOARD_AMD_BIRMAN_PHOENIX_FSP
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select BOARD_AMD_BIRMAN_COMMON
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select SOC_AMD_PHOENIX_FSP
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config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
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select BOARD_AMD_BIRMAN_COMMON
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select SOC_AMD_PHOENIX_OPENSIL
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config BOARD_AMD_BIRMAN_GLINDA
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select BOARD_AMD_BIRMAN_COMMON
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select SOC_AMD_GLINDA
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@ -27,7 +31,7 @@ if BOARD_AMD_BIRMAN_COMMON
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config FMDFILE
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default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA
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default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP
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default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS
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default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA
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default "src/mainboard/amd/birman/board_phoenix.fmd"
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@ -37,10 +41,12 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA
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default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP
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default "Birman_Phoenix_openSIL" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
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config DEVICETREE
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default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA
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default "devicetree_phoenix.cb"
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default "devicetree_phoenix_fsp.cb" if BOARD_AMD_BIRMAN_PHOENIX_FSP
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default "devicetree_phoenix_opensil.cb" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
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config BIRMAN_HAVE_MCHP_FW
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bool "Have Microchip EC firmware?"
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@ -3,5 +3,8 @@ comment "Birman"
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config BOARD_AMD_BIRMAN_PHOENIX_FSP
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bool "-> Birman for Phoenix SoC using FSP"
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config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
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bool "-> Birman for Phoenix SoC using openSIL"
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config BOARD_AMD_BIRMAN_GLINDA
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bool "-> Birman for Glinda SoC"
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@ -0,0 +1,144 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# TODO: Update for birman
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chip soc/amd/phoenix
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register "common_config.espi_config" = "{
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.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
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.generic_io_range[0] = {
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.base = 0x3f8,
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.size = 8,
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},
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.generic_io_range[1] = {
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.base = 0x600,
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.size = 256,
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},
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.io_mode = ESPI_IO_MODE_QUAD,
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.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
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.crc_check_enable = 1,
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.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
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.periph_ch_en = 1,
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.vw_ch_en = 1,
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.oob_ch_en = 1,
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.flash_ch_en = 0,
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}"
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register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
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GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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register "i2c[0].early_init" = "1"
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register "i2c[1].early_init" = "1"
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register "i2c[2].early_init" = "1"
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register "i2c[3].early_init" = "1"
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# I2C Pad Control RX Select Configuration
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register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
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register "s0ix_enable" = "true"
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register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works<
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device domain 0 on
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device ref iommu on end
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device ref gpp_bridge_1_1 on end # MXM
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device ref gpp_bridge_1_2 on
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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end
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end # NVMe SSD1
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device ref gpp_bridge_1_3 on end # GBE
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device ref gpp_bridge_2_1 on end # SD
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device ref gpp_bridge_2_2 on end # WWAN
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device ref gpp_bridge_2_3 on end # WIFI
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device ref gpp_bridge_2_4 on
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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end
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end # NVMe SSD0
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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device ref crypto on end # Crypto Coprocessor
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device ref xhci_0 on # USB 3.1 (USB0)
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chip drivers/usb/acpi
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device ref xhci_0_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port2 on end
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end
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chip drivers/usb/acpi
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device ref usb3_port3 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port6 on end
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end
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end
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end
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end
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device ref xhci_1 on # USB 3.1 (USB1)
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chip drivers/usb/acpi
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device ref xhci_1_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port7 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port7 on end
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end
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end
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end
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end
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device ref acp on end # Audio Processor (ACP)
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end
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device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
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device ref usb4_xhci_0 on
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chip drivers/usb/acpi
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device ref usb4_xhci_0_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port0 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port0 on end
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end
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end
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end
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end
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device ref usb4_xhci_1 on
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chip drivers/usb/acpi
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device ref usb4_xhci_1_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port1 on end
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end
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end
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end
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end
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end
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end
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device ref i2c_0 on end
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device ref i2c_1 on end
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device ref i2c_2 on end
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device ref i2c_3 on end
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device ref uart_0 on end # UART0
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end
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