From 0b87bb77261fc106d6473eba25202d719fd7b13d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 11 Nov 2014 17:22:23 +0200 Subject: [PATCH] AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPIO pins are shared with PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, simply setting 0:14.4 disabled in the devicetree does not work here yet. Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8495 Reviewed-by: Alexandru Gagniuc Reviewed-by: Nicolas Reinecke Tested-by: build bot (Jenkins) --- src/southbridge/amd/cimx/sb800/chip.h | 1 + src/southbridge/amd/cimx/sb800/late.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h index 2c2ce1ec13..f0ce0751c8 100644 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ b/src/southbridge/amd/cimx/sb800/chip.h @@ -35,6 +35,7 @@ struct southbridge_amd_cimx_sb800_config { u32 boot_switch_sata_ide : 1; + u32 disconnect_pcib : 1; u8 gpp_configuration; /* diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e01793607b..2125027083 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -401,7 +401,7 @@ static void sb800_enable(device_t dev) * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins * to function as GPIO {GPIO 35:0}. */ - if (dev->enabled) + if (!sb_chip->disconnect_pcib && dev->enabled) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); else RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);