google/glados: Convert to variant setup
Convert Skylake reference board glados to variant setup in preparation for merge with existing Skylake boards chell and lars, and upstreaming of new boards asuka, caroline, cave, and sentry. The following changes have been made: - move DPTF to variant subdir - move non-common EC defs to variant subdir - adjust Kconfig for variant setup - move non-common NHLT config to variant Kconfig - make non-common NHLT ACPI code conditional - move devicetree to variant subdir - move board GPIO defs to variant subdir - move board PEI data to variant subdir - move SPD index calculation to romstage so available for dual-channel determination during PEI for boards which need it - move SPD compilation to variant makefile - add weak function for determination of dual-channel RAM - add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants can override and power down rails as needed Test: build google/glados Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
86669939ea
commit
0b9cfe60b2
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@ -1,13 +1,11 @@
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if BOARD_GOOGLE_GLADOS
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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config BOARD_GOOGLE_BASEBOARD_GLADOS
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_NAU8825
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_LPC
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select EC_GOOGLE_CHROMEEC_MEC
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select EC_GOOGLE_CHROMEEC_PD
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@ -21,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOC_INTEL_SKYLAKE
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select SYSTEM_TYPE_LAPTOP
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if BOARD_GOOGLE_BASEBOARD_GLADOS
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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@ -35,12 +35,20 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "Glados"
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default "Glados" if BOARD_GOOGLE_GLADOS
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config MAINBOARD_FAMILY
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string
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default "Google_Glados"
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config VARIANT_DIR
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string
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default "glados" if BOARD_GOOGLE_GLADOS
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config DEVICETREE
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string
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default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
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config MAX_CPUS
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int
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default 8
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@ -52,20 +60,18 @@ config TPM_PIRQ
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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select NHLT_DMIC_2CH
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select NHLT_DMIC_4CH
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select NHLT_NAU88L25
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select NHLT_SSM4567
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config EC_GOOGLE_CHROMEEC_BOARDNAME
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string
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default "glados"
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default "glados" if BOARD_GOOGLE_GLADOS
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config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
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string
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default "glados_pd"
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default "glados_pd" if BOARD_GOOGLE_GLADOS
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config GBB_HWID
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string
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depends on CHROMEOS
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default "GLADOS TEST 1988"
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default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
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endif
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@ -1,2 +1,7 @@
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comment "Glados"
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config BOARD_GOOGLE_GLADOS
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bool "Glados"
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bool "-> Glados Skylake Reference Board"
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select BOARD_GOOGLE_BASEBOARD_GLADOS
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select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
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select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
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@ -17,7 +17,7 @@ subdirs-y += spd
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bootblock-y += bootblock_mainboard.c
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romstage-y += pei_data.c
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romstage-y += spd/spd.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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@ -27,7 +27,10 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
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ramstage-y += mainboard.c
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ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -14,77 +14,8 @@
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 90
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC1 80
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#define DPTF_CPU_ACTIVE_AC2 70
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#define DPTF_CPU_ACTIVE_AC3 60
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#define DPTF_CPU_ACTIVE_AC4 50
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/* Include Variant DPTF */
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#include <variant/acpi/dptf.asl>
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#define DPTF_TSR0_SENSOR_ID 1
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#define DPTF_TSR0_SENSOR_NAME "Ambient"
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#define DPTF_TSR0_PASSIVE 55
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#define DPTF_TSR0_CRITICAL 70
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#define DPTF_TSR1_SENSOR_ID 2
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#define DPTF_TSR1_SENSOR_NAME "Charger"
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#define DPTF_TSR1_PASSIVE 55
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR2_SENSOR_ID 3
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#define DPTF_TSR2_SENSOR_NAME "DRAM"
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#define DPTF_TSR2_PASSIVE 55
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#define DPTF_TSR2_CRITICAL 70
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#define DPTF_TSR3_SENSOR_ID 4
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#define DPTF_TSR3_SENSOR_NAME "WiFi"
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#define DPTF_TSR3_PASSIVE 55
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#define DPTF_TSR3_CRITICAL 70
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/* SKL-Y EC already has a custom charge profile based on temperature. */
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#undef DPTF_ENABLE_CHARGER
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/* SKL-Y is Fanless design. */
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#undef DPTF_ENABLE_FAN_CONTROL
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 2 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 3 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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6000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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8000, /* PowerLimitMinimum */
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8000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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/* Include DPTF */
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/* Include SoC DPTF */
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#include <soc/intel/skylake/acpi/dptf/dptf.asl>
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@ -15,13 +15,8 @@
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/* mainboard configuration */
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#include "../ec.h"
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#include "../gpio.h"
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed Keyboard Backlight in ACPI */
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#define EC_ENABLE_KEYBOARD_BACKLIGHT
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#include <variant/ec.h>
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#include <variant/gpio.h>
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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@ -13,8 +13,6 @@
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* GNU General Public License for more details.
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*/
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#include "../gpio.h"
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Scope (\_SB)
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{
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Device (PWRB)
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@ -22,3 +20,6 @@ Scope (\_SB)
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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/* Variant-specific ACPI, including USB port defs */
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#include <variant/acpi/mainboard.asl>
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*/
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/* mainboard configuration */
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#include "../ec.h"
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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@ -14,14 +14,13 @@
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* GNU General Public License for more details.
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*/
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#include <bootmode.h>
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#include <rules.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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*/
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#include <arch/acpi.h>
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#include <baseboard/variant.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <stdlib.h>
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printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
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/* 4 Channel DMIC array. */
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if (nhlt_soc_add_dmic_array(nhlt, 4))
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printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
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if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH))
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if (nhlt_soc_add_dmic_array(nhlt, 4))
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printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
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/* ADI Smart Amps for left and right. */
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if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
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printk(BIOS_ERR, "Couldn't add ssm4567.\n");
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if (IS_ENABLED(CONFIG_NHLT_SSM4567))
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if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
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printk(BIOS_ERR, "Couldn't add ssm4567.\n");
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/* NAU88l25 Headset codec. */
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if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
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@ -15,7 +15,7 @@
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*/
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#include <soc/ramstage.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
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{
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@ -17,13 +17,24 @@
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#include <string.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include <soc/romstage.h>
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#include "spd/spd.h"
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#include <variant/gpio.h>
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void mainboard_romstage_entry(struct romstage_params *params)
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{
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/* Get SPD index */
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gpio_t spd_gpios[] = {
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GPIO_MEM_CONFIG_0,
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GPIO_MEM_CONFIG_1,
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GPIO_MEM_CONFIG_2,
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GPIO_MEM_CONFIG_3,
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};
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params->pei_data->mem_cfg_id =
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gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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/* Fill out PEI DATA */
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mainboard_fill_pei_data(params->pei_data);
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mainboard_fill_spd_data(params->pei_data);
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@ -16,6 +16,7 @@
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <baseboard/variant.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <elog.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include "gpio.h"
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#include <variant/gpio.h>
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int mainboard_io_trap_handler(int smif)
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{
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@ -54,21 +55,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
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chromeec_smi_process_events();
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}
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static void mainboard_gpio_smi_sleep(u8 slp_typ)
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__weak void mainboard_gpio_smi_sleep(void)
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{
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int i;
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/* Power down the rails on any sleep type. */
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gpio_t active_high_signals[] = {
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EN_PP3300_KEPLER,
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EN_PP3300_DX_TOUCH,
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EN_PP3300_DX_EMMC,
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EN_PP1800_DX_EMMC,
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EN_PP3300_DX_CAM,
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};
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for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
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gpio_set(active_high_signals[i], 0);
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}
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void mainboard_smi_sleep(u8 slp_typ)
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@ -77,7 +65,7 @@ void mainboard_smi_sleep(u8 slp_typ)
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
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MAINBOARD_EC_S5_WAKE_EVENTS);
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mainboard_gpio_smi_sleep(slp_typ);
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mainboard_gpio_smi_sleep();
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}
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int mainboard_smi_apmc(u8 apmc)
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@ -22,8 +22,7 @@
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#include <soc/pei_data.h>
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#include <soc/romstage.h>
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#include <string.h>
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#include "../gpio.h"
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#include <baseboard/variant.h>
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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@ -77,6 +76,12 @@ static void mainboard_print_spd_info(uint8_t spd[])
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}
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}
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__weak int is_dual_channel(const int spd_index)
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{
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/* default to dual channel */
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return 1;
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}
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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@ -84,14 +89,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
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size_t spd_file_len;
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int spd_index;
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gpio_t spd_gpios[] = {
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GPIO_MEM_CONFIG_0,
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GPIO_MEM_CONFIG_1,
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GPIO_MEM_CONFIG_2,
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GPIO_MEM_CONFIG_3,
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};
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spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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spd_index = pei_data->mem_cfg_id;
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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/* Load SPD data from CBFS */
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@ -113,7 +111,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
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/* Assume same memory in both channels */
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spd_index *= SPD_LEN;
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memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
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memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
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if (is_dual_channel(spd_index))
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memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
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/* Make sure a valid SPD was found */
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if (pei_data->spd_data[0][0][0] == 0)
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
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* the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#ifndef GLADOS_VARIANT_H
|
||||
#define GLADOS_VARIANT_H
|
||||
|
||||
int is_dual_channel(const int spd_index);
|
||||
void mainboard_gpio_smi_sleep(void);
|
||||
|
||||
#endif /* GLADOS_VARIANT_H */
|
|
@ -14,7 +14,9 @@
|
|||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
romstage-y += variant.c
|
||||
ramstage-y += variant.c
|
||||
smm-y += variant.c
|
||||
|
||||
SPD_BIN = $(obj)/spd.bin
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 80
|
||||
#define DPTF_CPU_CRITICAL 90
|
||||
#define DPTF_CPU_ACTIVE_AC0 90
|
||||
#define DPTF_CPU_ACTIVE_AC1 80
|
||||
#define DPTF_CPU_ACTIVE_AC2 70
|
||||
#define DPTF_CPU_ACTIVE_AC3 60
|
||||
#define DPTF_CPU_ACTIVE_AC4 50
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 1
|
||||
#define DPTF_TSR0_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR0_PASSIVE 55
|
||||
#define DPTF_TSR0_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 2
|
||||
#define DPTF_TSR1_SENSOR_NAME "Charger"
|
||||
#define DPTF_TSR1_PASSIVE 55
|
||||
#define DPTF_TSR1_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 3
|
||||
#define DPTF_TSR2_SENSOR_NAME "DRAM"
|
||||
#define DPTF_TSR2_PASSIVE 55
|
||||
#define DPTF_TSR2_CRITICAL 70
|
||||
|
||||
#define DPTF_TSR3_SENSOR_ID 4
|
||||
#define DPTF_TSR3_SENSOR_NAME "WiFi"
|
||||
#define DPTF_TSR3_PASSIVE 55
|
||||
#define DPTF_TSR3_CRITICAL 70
|
||||
|
||||
/* SKL-Y EC already has a custom charge profile based on temperature. */
|
||||
#undef DPTF_ENABLE_CHARGER
|
||||
|
||||
/* SKL-Y is Fanless design. */
|
||||
#undef DPTF_ENABLE_FAN_CONTROL
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 1 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 2 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 3 */
|
||||
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
1600, /* PowerLimitMinimum */
|
||||
6000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
8000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable EC backed Keyboard Backlight in ACPI */
|
||||
#define EC_ENABLE_KEYBOARD_BACKLIGHT
|
|
@ -14,10 +14,13 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variant.h>
|
||||
#include <gpio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
|
@ -45,3 +48,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
|
|||
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||
sizeof(RcompTarget));
|
||||
}
|
||||
|
||||
void mainboard_gpio_smi_sleep(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Power down the rails on any sleep type. */
|
||||
gpio_t active_high_signals[] = {
|
||||
EN_PP3300_KEPLER,
|
||||
EN_PP3300_DX_TOUCH,
|
||||
EN_PP3300_DX_EMMC,
|
||||
EN_PP1800_DX_EMMC,
|
||||
EN_PP3300_DX_CAM,
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
|
||||
gpio_set(active_high_signals[i], 0);
|
||||
}
|
Loading…
Reference in New Issue