google/glados: Convert to variant setup

Convert Skylake reference board glados to variant setup in
preparation for merge with existing Skylake boards chell and lars,
and upstreaming of new boards asuka, caroline, cave, and sentry.

The following changes have been made:
- move DPTF to variant subdir
- move non-common EC defs to variant subdir
- adjust Kconfig for variant setup
- move non-common NHLT config to variant Kconfig
- make non-common NHLT ACPI code conditional
- move devicetree to variant subdir
- move board GPIO defs to variant subdir
- move board PEI data to variant subdir
- move SPD index calculation to romstage so available for
    dual-channel determination during PEI for boards which need it
- move SPD compilation to variant makefile
- add weak function for determination of dual-channel RAM
- add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants
    can override and power down rails as needed

Test: build google/glados

Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/glados/Kconfig

@@ -1,13 +1,11 @@
-if BOARD_GOOGLE_GLADOS
+config BOARD_GOOGLE_BASEBOARD_GLADOS
-
+	def_bool n
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_NAU8825
 	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
+	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
 	select EC_GOOGLE_CHROMEEC_PD
@@ -21,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_INTEL_SKYLAKE
 	select SYSTEM_TYPE_LAPTOP
 
+if BOARD_GOOGLE_BASEBOARD_GLADOS
+
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH
@@ -35,12 +35,20 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Glados"
+	default "Glados" if BOARD_GOOGLE_GLADOS
 
 config MAINBOARD_FAMILY
 	string
 	default "Google_Glados"
 
+config VARIANT_DIR
+	string
+	default "glados" if BOARD_GOOGLE_GLADOS
+
+config DEVICETREE
+	string
+	default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
+
 config MAX_CPUS
 	int
 	default 8
@@ -52,20 +60,18 @@ config TPM_PIRQ
 config INCLUDE_NHLT_BLOBS
 	bool "Include blobs for audio."
 	select NHLT_DMIC_2CH
-	select NHLT_DMIC_4CH
 	select NHLT_NAU88L25
-	select NHLT_SSM4567
 
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string
-	default "glados"
+	default "glados" if BOARD_GOOGLE_GLADOS
 
 config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
 	string
-	default "glados_pd"
+	default "glados_pd" if BOARD_GOOGLE_GLADOS
 
 config GBB_HWID
 	string
 	depends on CHROMEOS
-	default "GLADOS TEST 1988"
+	default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
 endif

src/mainboard/google/glados/Kconfig.name

@@ -1,2 +1,7 @@
+comment "Glados"
+
 config BOARD_GOOGLE_GLADOS
-	bool "Glados"
+	bool "->  Glados Skylake Reference Board"
+	select BOARD_GOOGLE_BASEBOARD_GLADOS
+	select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
+	select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS

src/mainboard/google/glados/Makefile.inc

@@ -17,7 +17,7 @@ subdirs-y += spd
 
 bootblock-y += bootblock_mainboard.c
 
-romstage-y += pei_data.c
+romstage-y += spd/spd.c
 
 bootblock-$(CONFIG_CHROMEOS) += chromeos.c
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -27,7 +27,10 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 
 ramstage-y += mainboard.c
-ramstage-y += pei_data.c
 ramstage-y += ramstage.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/google/glados/acpi/dptf.asl

@@ -14,77 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_CPU_PASSIVE        80
+/* Include Variant DPTF */
-#define DPTF_CPU_CRITICAL       90
+#include <variant/acpi/dptf.asl>
-#define DPTF_CPU_ACTIVE_AC0     90
-#define DPTF_CPU_ACTIVE_AC1     80
-#define DPTF_CPU_ACTIVE_AC2     70
-#define DPTF_CPU_ACTIVE_AC3     60
-#define DPTF_CPU_ACTIVE_AC4     50
 
-#define DPTF_TSR0_SENSOR_ID	1
+/* Include SoC DPTF */
-#define DPTF_TSR0_SENSOR_NAME	"Ambient"
-#define DPTF_TSR0_PASSIVE	55
-#define DPTF_TSR0_CRITICAL	70
-
-#define DPTF_TSR1_SENSOR_ID	2
-#define DPTF_TSR1_SENSOR_NAME	"Charger"
-#define DPTF_TSR1_PASSIVE	55
-#define DPTF_TSR1_CRITICAL	70
-
-#define DPTF_TSR2_SENSOR_ID	3
-#define DPTF_TSR2_SENSOR_NAME	"DRAM"
-#define DPTF_TSR2_PASSIVE	55
-#define DPTF_TSR2_CRITICAL	70
-
-#define DPTF_TSR3_SENSOR_ID	4
-#define DPTF_TSR3_SENSOR_NAME	"WiFi"
-#define DPTF_TSR3_PASSIVE	55
-#define DPTF_TSR3_CRITICAL	70
-
-/* SKL-Y EC already has a custom charge profile based on temperature. */
-#undef DPTF_ENABLE_CHARGER
-
-/* SKL-Y is Fanless design. */
-#undef DPTF_ENABLE_FAN_CONTROL
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 2 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 3 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		1600,	/* PowerLimitMinimum */
-		6000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		8000,	/* PowerLimitMinimum */
-		8000,	/* PowerLimitMaximum */
-		1000,	/* TimeWindowMinimum */
-		1000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})
-
-/* Include DPTF */
 #include <soc/intel/skylake/acpi/dptf/dptf.asl>

src/mainboard/google/glados/acpi/ec.asl

@@ -15,13 +15,8 @@
 
 /* mainboard configuration */
 #include "../ec.h"
-#include "../gpio.h"
+#include <variant/ec.h>
-
+#include <variant/gpio.h>
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed Keyboard Backlight in ACPI */
-#define EC_ENABLE_KEYBOARD_BACKLIGHT
 
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE

src/mainboard/google/glados/acpi/mainboard.asl

@@ -13,8 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include "../gpio.h"
-
 Scope (\_SB)
 {
 	Device (PWRB)
@@ -22,3 +20,6 @@ Scope (\_SB)
 		Name (_HID, EisaId ("PNP0C0C"))
 	}
 }
+
+/* Variant-specific ACPI, including USB port defs */
+#include <variant/acpi/mainboard.asl>

src/mainboard/google/glados/acpi/superio.asl

@@ -14,8 +14,6 @@
  */
 
 /* mainboard configuration */
-#include "../ec.h"
-
 #define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
 #define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
 #define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard

src/mainboard/google/glados/bootblock_mainboard.c

@@ -15,7 +15,7 @@
 
 #include <bootblock_common.h>
 #include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 static void early_config_gpio(void)
 {

src/mainboard/google/glados/chromeos.c

@@ -14,14 +14,13 @@
  * GNU General Public License for more details.
  */
 
-#include <bootmode.h>
 #include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#include "gpio.h"
+#include <variant/gpio.h>
 
 #if ENV_RAMSTAGE
 #include <boot/coreboot_tables.h>

src/mainboard/google/glados/mainboard.c

@@ -16,6 +16,7 @@
  */
 
 #include <arch/acpi.h>
+#include <baseboard/variant.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <stdlib.h>
@@ -47,10 +48,12 @@ static unsigned long mainboard_write_acpi_tables(
 		printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
 
 	/* 4 Channel DMIC array. */
+	if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH))
 		if (nhlt_soc_add_dmic_array(nhlt, 4))
 			printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
 
 	/* ADI Smart Amps for left and right. */
+	if (IS_ENABLED(CONFIG_NHLT_SSM4567))
 		if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
 			printk(BIOS_ERR, "Couldn't add ssm4567.\n");
 

src/mainboard/google/glados/ramstage.c

@@ -15,7 +15,7 @@
  */
 
 #include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
 {

src/mainboard/google/glados/romstage.c

@@ -17,13 +17,24 @@
 
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
+#include <gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 #include <soc/romstage.h>
 #include "spd/spd.h"
+#include <variant/gpio.h>
 
 void mainboard_romstage_entry(struct romstage_params *params)
 {
+	/* Get SPD index */
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+	params->pei_data->mem_cfg_id =
+			gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 	/* Fill out PEI DATA */
 	mainboard_fill_pei_data(params->pei_data);
 	mainboard_fill_spd_data(params->pei_data);

src/mainboard/google/glados/smihandler.c

@@ -16,6 +16,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <baseboard/variant.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
@@ -26,7 +27,7 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 #include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
 
 int mainboard_io_trap_handler(int smif)
 {
@@ -54,21 +55,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 		chromeec_smi_process_events();
 }
 
-static void mainboard_gpio_smi_sleep(u8 slp_typ)
+__weak void mainboard_gpio_smi_sleep(void)
 {
-	int i;
-
-	/* Power down the rails on any sleep type. */
-	gpio_t active_high_signals[] = {
-		EN_PP3300_KEPLER,
-		EN_PP3300_DX_TOUCH,
-		EN_PP3300_DX_EMMC,
-		EN_PP1800_DX_EMMC,
-		EN_PP3300_DX_CAM,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
-		gpio_set(active_high_signals[i], 0);
 }
 
 void mainboard_smi_sleep(u8 slp_typ)
@@ -77,7 +65,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 		chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
 					MAINBOARD_EC_S5_WAKE_EVENTS);
 
-	mainboard_gpio_smi_sleep(slp_typ);
+	mainboard_gpio_smi_sleep();
 }
 
 int mainboard_smi_apmc(u8 apmc)

src/mainboard/google/glados/spd/spd.c

@@ -22,8 +22,7 @@
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <string.h>
-
+#include <baseboard/variant.h>
-#include "../gpio.h"
 #include "spd.h"
 
 static void mainboard_print_spd_info(uint8_t spd[])
@@ -77,6 +76,12 @@ static void mainboard_print_spd_info(uint8_t spd[])
 	}
 }
 
+__weak int is_dual_channel(const int spd_index)
+{
+	/* default to dual channel */
+	return 1;
+}
+
 /* Copy SPD data for on-board memory */
 void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
@@ -84,14 +89,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	size_t spd_file_len;
 	int spd_index;
 
-	gpio_t spd_gpios[] = {
+	spd_index = pei_data->mem_cfg_id;
-		GPIO_MEM_CONFIG_0,
-		GPIO_MEM_CONFIG_1,
-		GPIO_MEM_CONFIG_2,
-		GPIO_MEM_CONFIG_3,
-	};
-
-	spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 	printk(BIOS_INFO, "SPD index %d\n", spd_index);
 
 	/* Load SPD data from CBFS */
@@ -113,6 +111,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	/* Assume same memory in both channels */
 	spd_index *= SPD_LEN;
 	memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
+	if (is_dual_channel(spd_index))
 		memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
 
 	/* Make sure a valid SPD was found */

src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GLADOS_VARIANT_H
+#define GLADOS_VARIANT_H
+
+int is_dual_channel(const int spd_index);
+void mainboard_gpio_smi_sleep(void);
+
+#endif /* GLADOS_VARIANT_H */

src/mainboard/google/glados/variants/glados/Makefile.inc

@@ -14,7 +14,9 @@
 ## GNU General Public License for more details.
 ##
 
-romstage-y += spd.c
+romstage-y += variant.c
+ramstage-y += variant.c
+smm-y += variant.c
 
 SPD_BIN = $(obj)/spd.bin
 

src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl

@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"Ambient"
+#define DPTF_TSR0_PASSIVE	55
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"Charger"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"DRAM"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_TSR3_SENSOR_ID	4
+#define DPTF_TSR3_SENSOR_NAME	"WiFi"
+#define DPTF_TSR3_PASSIVE	55
+#define DPTF_TSR3_CRITICAL	70
+
+/* SKL-Y EC already has a custom charge profile based on temperature. */
+#undef DPTF_ENABLE_CHARGER
+
+/* SKL-Y is Fanless design. */
+#undef DPTF_ENABLE_FAN_CONTROL
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 3 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})

src/mainboard/google/glados/variants/glados/include/variant/ec.h

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT

src/mainboard/google/glados/variants/glados/variant.c

@@ -14,10 +14,13 @@
  * GNU General Public License for more details.
  */
 
+#include <baseboard/variant.h>
+#include <gpio.h>
 #include <stdint.h>
 #include <string.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
+#include <variant/gpio.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
@@ -45,3 +48,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	memcpy(pei_data->RcompTarget, RcompTarget,
 		 sizeof(RcompTarget));
 }
+
+void mainboard_gpio_smi_sleep(void)
+{
+	int i;
+
+	/* Power down the rails on any sleep type. */
+	gpio_t active_high_signals[] = {
+		EN_PP3300_KEPLER,
+		EN_PP3300_DX_TOUCH,
+		EN_PP3300_DX_EMMC,
+		EN_PP1800_DX_EMMC,
+		EN_PP3300_DX_CAM,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
+		gpio_set(active_high_signals[i], 0);
+}