mb/kontron/bsl6: Remove disabled devices from devicetrees

All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.

Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Felix Singer 2020-12-24 07:46:21 +01:00 committed by Nico Huber
parent 4925d1c282
commit 0ba8213d4c
2 changed files with 0 additions and 24 deletions

View File

@ -82,17 +82,8 @@ chip soc/intel/skylake
register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"
register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 off end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on # SATA
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
@ -100,11 +91,6 @@ chip soc/intel/skylake
register "SataPortsEnable[2]" = "1"
# SataPortsDevSlp not supported
end
device pci 19.0 off end # UART #2
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9 (COMe 0)
register "PcieRpEnable[8]" = "1"
end
@ -114,10 +100,6 @@ chip soc/intel/skylake
device pci 1d.2 on # PCI Express Port 11 (COMe 2)
register "PcieRpEnable[10]" = "1"
end
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@ -134,7 +116,6 @@ chip soc/intel/skylake
end
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 off end # Intel HDA
device pci 1f.4 on # SMBus
chip drivers/i2c/nct7802y
device i2c 0x2e on end

View File

@ -5,11 +5,6 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
device domain 0 on
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1d.3 off end # PCI Express Port 12
device pci 1f.0 on
chip ec/kontron/kempld
device generic 1.0 on # I2C