mb/kontron/bsl6: Remove disabled devices from devicetrees
All known on-chip PCI devices are documented in chipset devicetree now and default to disabled. There is no need to keep disabled PCI devices in the mainboard's devicetree. Thus, remove them. Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -82,17 +82,8 @@ chip soc/intel/skylake
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register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"
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register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"
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register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug
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register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug
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end
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on # SATA
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device pci 17.0 on # SATA
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register "SataSalpSupport" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[0]" = "1"
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@ -100,11 +91,6 @@ chip soc/intel/skylake
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[2]" = "1"
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# SataPortsDevSlp not supported
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# SataPortsDevSlp not supported
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end
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end
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device pci 19.0 off end # UART #2
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9 (COMe 0)
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device pci 1d.0 on # PCI Express Port 9 (COMe 0)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[8]" = "1"
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end
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end
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@ -114,10 +100,6 @@ chip soc/intel/skylake
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device pci 1d.2 on # PCI Express Port 11 (COMe 2)
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device pci 1d.2 on # PCI Express Port 11 (COMe 2)
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register "PcieRpEnable[10]" = "1"
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register "PcieRpEnable[10]" = "1"
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end
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end
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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device pci 1f.0 on # LPC Interface
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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@ -134,7 +116,6 @@ chip soc/intel/skylake
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on # SMBus
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device pci 1f.4 on # SMBus
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chip drivers/i2c/nct7802y
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chip drivers/i2c/nct7802y
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device i2c 0x2e on end
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device i2c 0x2e on end
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@ -5,11 +5,6 @@ chip soc/intel/skylake
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register "SkipExtGfxScan" = "1"
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register "SkipExtGfxScan" = "1"
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device domain 0 on
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device domain 0 on
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1f.0 on
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device pci 1f.0 on
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chip ec/kontron/kempld
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chip ec/kontron/kempld
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device generic 1.0 on # I2C
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device generic 1.0 on # I2C
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