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mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices 

Add the subsystem ids to PCI ports and devices, which were dumped on
vendor firmware using `lspci`.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-05 22:48:41 +01:00
parent fb7a06b5b7
commit 0bae5a72c5
1 changed files with 7 additions and 2 deletions
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9
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -44,6 +44,7 @@ chip soc/intel/skylake
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on device domain 0 on
subsystemid 0x15d9 0x0896 inherit
device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
end end
@ -63,12 +64,16 @@ chip soc/intel/skylake
device pci 1d.0 on # PCH PCIe Port 9 device pci 1d.0 on # PCH PCIe Port 9
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
device pci 00.0 on end # GbE 1 device pci 00.0 on # GbE 1
subsystemid 0x15d9 0x1533
end
end end
device pci 1d.1 on # PCH PCIe Port 10 device pci 1d.1 on # PCH PCIe Port 10
register "PcieRpEnable[9]" = "1" register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1"
device pci 00.1 on end # GbE 2 device pci 00.0 on # GbE 2
subsystemid 0x15d9 0x1533
end
end end
device pci 1d.2 on # PCH PCIe Port 11 device pci 1d.2 on # PCH PCIe Port 11
register "PcieRpEnable[10]" = "1" register "PcieRpEnable[10]" = "1"