Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
3693266d0d
commit
0bafd964b7
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@ -1,198 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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DefinitionBlock (
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"DSDT.AML",
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"DSDT",
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0x01,
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"XXXXXX",
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"XXXXXXXX",
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0x00010001
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)
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{
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#include "debug.asl"
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}
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*/
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/*
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* 0x80: POST_BASE
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* 0x3F8: DEBCOM_BASE
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* X80: POST_REGION
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* P80: PORT80
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*
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* CREG: DEBCOM_REGION
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* CUAR: DEBCOM_UART
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* CDAT: DEBCOM_DATA
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* CDLM: DEBCOM_DLM
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* DLCR: DEBCOM_LCR
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* CMCR: DEBCOM_MCR
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* CLSR: DEBCOM_LSR
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*
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* DEBUG_INIT DINI
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*/
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OperationRegion(X80, SystemIO, 0x80, 1)
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Field(X80, ByteAcc, NoLock, Preserve)
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{
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P80, 8
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}
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OperationRegion(CREG, SystemIO, 0x3F8, 8)
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Field(CREG, ByteAcc, NoLock, Preserve)
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{
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CDAT, 8,
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CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
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}
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/*
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* DINI
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* Initialize the COM port to 115,200 8-N-1
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*/
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Method(DINI)
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{
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store(0x83, DLCR)
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store(0x01, CDAT) /* 115200 baud (low) */
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store(0x00, CDLM) /* 115200 baud (high) */
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store(0x03, DLCR) /* word=8 stop=1 parity=none */
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store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */
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store(0x00, CDLM) /* turn off interrupts */
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}
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/*
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* THRE
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* Wait for COM port transmitter holding register to go empty
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*/
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Method(THRE)
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{
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and(CLSR, 0x20, local0)
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while (Lequal(local0, Zero)) {
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and(CLSR, 0x20, local0)
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}
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}
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/*
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* OUTX
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* Send a single raw character
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*/
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Method(OUTX, 1)
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{
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THRE()
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store(Arg0, CDAT)
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}
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/*
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* OUTC
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* Send a single character, expanding LF into CR/LF
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*/
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Method(OUTC, 1)
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{
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if (LEqual(Arg0, 0x0a)) {
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OUTX(0x0d)
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}
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OUTX(Arg0)
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}
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/*
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* DBGN
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* Send a single hex nibble
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*/
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Method(DBGN, 1)
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{
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and(Arg0, 0x0f, Local0)
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if (LLess(Local0, 10)) {
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add(Local0, 0x30, Local0)
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} else {
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add(Local0, 0x37, Local0)
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}
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OUTC(Local0)
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}
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/*
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* DBGB
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* Send a hex byte
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*/
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Method(DBGB, 1)
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{
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ShiftRight(Arg0, 4, Local0)
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DBGN(Local0)
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DBGN(Arg0)
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}
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/*
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* DBGW
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* Send a hex word
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*/
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Method(DBGW, 1)
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{
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ShiftRight(Arg0, 8, Local0)
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DBGB(Local0)
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DBGB(Arg0)
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}
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/*
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* DBGD
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* Send a hex Dword
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*/
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Method(DBGD, 1)
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{
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ShiftRight(Arg0, 16, Local0)
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DBGW(Local0)
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DBGW(Arg0)
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}
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/*
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* DBGO
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* Send either a string or an integer
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*/
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Method(DBGO, 1)
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{
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/* DINI() */
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if (LEqual(ObjectType(Arg0), 1)) {
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if (LGreater(Arg0, 0xffff)) {
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DBGD(Arg0)
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} else {
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if (LGreater(Arg0, 0xff)) {
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DBGW(Arg0)
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} else {
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DBGB(Arg0)
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}
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}
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} else {
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Name(BDBG, Buffer(80) {})
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store(Arg0, BDBG)
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store(0, Local1)
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while (One) {
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store(GETC(BDBG, Local1), Local0)
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if (LEqual(Local0, 0)) {
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return (0)
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}
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OUTC(Local0)
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Increment(Local1)
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}
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}
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return (0)
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}
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/* Get a char from a string */
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Method(GETC, 2)
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{
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CreateByteField(Arg0, Arg1, DBGC)
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return (DBGC)
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}
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@ -1,244 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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Scope (_SB) {
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Device(PCI0) {
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Device(IDEC) {
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Name(_ADR, 0x00140001)
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#include "ide.asl"
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}
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}
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}
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*/
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/* Some timing tables */
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Name(UDTT, Package(){ /* Udma timing table */
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120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
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})
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Name(MDTT, Package(){ /* MWDma timing table */
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480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
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})
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Name(POTT, Package(){ /* Pio timing table */
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600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
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})
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/* Some timing register value tables */
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Name(MDRT, Package(){ /* MWDma timing register table */
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0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
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})
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Name(PORT, Package(){
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0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
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})
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OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
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Field(ICRG, AnyAcc, NoLock, Preserve)
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{
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PPTS, 8, /* Primary PIO Slave Timing */
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PPTM, 8, /* Primary PIO Master Timing */
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OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
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PMTM, 8, /* Primary MWDMA Master Timing */
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OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
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OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
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PPSM, 4, /* Primary PIO slave Mode */
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OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
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OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
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PDSM, 4, /* Primary UltraDMA Mode */
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}
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Method(GTTM, 1) /* get total time*/
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{
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Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
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Increment(Local0)
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Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
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Increment(Local1)
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Return(Multiply(30, Add(Local0, Local1)))
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}
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Device(PRID)
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{
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Name (_ADR, Zero)
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Method(_GTM, 0)
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{
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NAME(OTBF, Buffer(20) { /* out buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
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CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
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/* Just return if the channel is disabled */
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If(And(PPCR, 0x01)) { /* primary PIO control */
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Return(OTBF)
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}
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/* Always tell them independent timing available and IOChannelReady used on both drives */
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Or(BFFG, 0x1A, BFFG)
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Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
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Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
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If(And(PDCR, 0x01)) { /* It's under UDMA mode */
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Or(BFFG, 0x01, BFFG)
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Store(DerefOf(Index(UDTT, PDMM)), DSD0)
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}
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Else {
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Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
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}
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If(And(PDCR, 0x02)) { /* It's under UDMA mode */
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Or(BFFG, 0x04, BFFG)
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Store(DerefOf(Index(UDTT, PDSM)), DSD1)
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}
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Else {
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Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
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}
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Return(OTBF) /* out buffer */
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} /* End Method(_GTM) */
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Method(_STM, 3, NotSerialized)
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{
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NAME(INBF, Buffer(20) { /* in buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
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CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(INBF, 16, BFFG) /*buffer flag */
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Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
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Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
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Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
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Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
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Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
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Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
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|
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If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDMM,)
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Or(PDCR, 0x01, PDCR)
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}
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Else {
|
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If(LNotEqual(DSD0, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTM)
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}
|
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}
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|
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If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDSM,)
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Or(PDCR, 0x02, PDCR)
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}
|
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Else {
|
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If(LNotEqual(DSD1, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTS)
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}
|
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}
|
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/* Return(INBF) */
|
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} /*End Method(_STM) */
|
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Device(MST)
|
||||
{
|
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Name(_ADR, 0)
|
||||
Method(_GTF) {
|
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Name(CMBF, Buffer(21) {
|
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
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CreateByteField(CMBF, 1, POMD)
|
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CreateByteField(CMBF, 8, DMMD)
|
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CreateByteField(CMBF, 5, CMDA)
|
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CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xA0, CMDA)
|
||||
Store(0xA0, CMDB)
|
||||
Store(0xA0, CMDC)
|
||||
|
||||
Or(PPMM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x01)) {
|
||||
Or(PDMM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTM),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(MST) */
|
||||
|
||||
Device(SLAV)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_GTF) {
|
||||
Name(CMBF, Buffer(21) {
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||
})
|
||||
CreateByteField(CMBF, 1, POMD)
|
||||
CreateByteField(CMBF, 8, DMMD)
|
||||
CreateByteField(CMBF, 5, CMDA)
|
||||
CreateByteField(CMBF, 12, CMDB)
|
||||
CreateByteField(CMBF, 19, CMDC)
|
||||
|
||||
Store(0xB0, CMDA)
|
||||
Store(0xB0, CMDB)
|
||||
Store(0xB0, CMDC)
|
||||
|
||||
Or(PPSM, 0x08, POMD)
|
||||
|
||||
If(And(PDCR, 0x02)) {
|
||||
Or(PDSM, 0x40, DMMD)
|
||||
}
|
||||
Else {
|
||||
Store(Match
|
||||
(MDTT, MLE, GTTM(PMTS),
|
||||
MTR, 0, 0), Local0)
|
||||
If(LLess(Local0, 3)) {
|
||||
Or(0x20, Local0, DMMD)
|
||||
}
|
||||
}
|
||||
Return(CMBF)
|
||||
}
|
||||
} /* End Device(SLAV) */
|
||||
}
|
||||
|
|
@ -1,149 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00120000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,161 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue