diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 7a169025e4..e77a3dc114 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -559,6 +559,10 @@ struct soc_intel_alderlake_config {
 	 * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values
 	 */
 	uint8_t SlowSlewRate[NUM_VR_DOMAINS];
+
+	/* Energy-Performance Preference (HWP feature) */
+	bool enable_energy_perf_pref;
+	uint8_t energy_perf_pref_value;
 };
 
 typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 66db16b6ed..7d4fb9cdf2 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -122,6 +122,11 @@ void soc_core_init(struct device *cpu)
 	/* Set energy policy */
 	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 
+	const config_t *conf = config_of_soc();
+	/* Set energy-performance preference */
+	if (conf->enable_energy_perf_pref)
+		if (check_energy_perf_cap())
+			set_energy_perf_pref(conf->energy_perf_pref_value);
 	/* Enable Turbo */
 	enable_turbo();
 }
@@ -132,6 +137,19 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 }
 
+static void pre_mp_init(void)
+{
+	soc_fsp_load();
+
+	const config_t *conf = config_of_soc();
+	if (conf->enable_energy_perf_pref) {
+		if (check_energy_perf_cap())
+			enable_energy_perf_pref();
+		else
+			printk(BIOS_WARNING, "Energy Performance Preference not supported!\n");
+	}
+}
+
 static void post_mp_init(void)
 {
 	/* Set Max Ratio */
@@ -152,7 +170,7 @@ static const struct mp_ops mp_ops = {
 	 * that are set prior to ramstage.
 	 * Real MTRRs programming are being done after resource allocation.
 	 */
-	.pre_mp_init = soc_fsp_load,
+	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = smm_info,
 	.get_microcode_info = get_microcode_info,