diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 59aa2214bc..ad4992803c 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -173,7 +173,6 @@ static uint32_t fetch_instruction(uintptr_t vaddr) {
 
 void handle_misaligned_load(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr:      %p\n", tf);
-	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void*) tf->gpr[2]);
 	uintptr_t faultingInstructionAddr = tf->epc;
 	insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
 	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
@@ -203,7 +202,6 @@ void handle_misaligned_load(trapframe *tf) {
 
 void handle_misaligned_store(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr:      %p\n", tf);
-	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void*) tf->gpr[2]);
 	uintptr_t faultingInstructionAddr = tf->epc;
 	insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
 	printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);