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mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch 

On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.

This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.

BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles

Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2019-09-25 11:41:15 +08:00 committed by Patrick Georgi
parent 58e96705cb
commit 0bc35af933
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -58,6 +58,8 @@ chip soc/intel/cannonlake
register "PmTimerDisabled" = "1" register "PmTimerDisabled" = "1"
register "PchPmSlpS0Vm075VSupport" = "1"
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+ #+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS | #| Domain/Setting | SA | IA | GTUS | GTS |