GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch 

This patch provides an option to enable or disable IPU (image processing unit),
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on devicetree entry.

Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
V Sowmya 2019-01-07 13:11:29 +05:30 committed by Patrick Georgi
parent 26a52f492b
commit 0bc3e3d590
2 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/cannonlake/include/soc/pci_devs.h
View File

@ -47,6 +47,10 @@
#define SA_DEVFN_DSP _SA_DEVFN(DSP) #define SA_DEVFN_DSP _SA_DEVFN(DSP)
#define SA_DEV_DSP _SA_DEV(DSP) #define SA_DEV_DSP _SA_DEV(DSP)
#define SA_DEV_SLOT_IPU 0x05
#define SA_DEVFN_IPU _SA_DEVFN(IPU)
#define SA_DEV_IPU _SA_DEV(IPU)
/* PCH Devices */ /* PCH Devices */
#define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEV_SLOT_THERMAL 0x12
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)

5
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -67,6 +67,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
else else
m_cfg->PchHdaEnable = dev->enabled; m_cfg->PchHdaEnable = dev->enabled;
/* Enable IPU only if the device is enabled */
m_cfg->SaIpuEnable = 0;
dev = pcidev_path_on_root(SA_DEVFN_IPU);
if (dev)
m_cfg->SaIpuEnable = dev->enabled;
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)