src/{drivers,soc}: Fix some code indents
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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@ -20,7 +20,7 @@ static void set_range_uc(u32 base, u32 size)
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for (i = 0; i < max_var_mtrrs; i++) {
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for (i = 0; i < max_var_mtrrs; i++) {
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msr = rdmsr(MTRR_PHYS_MASK(i));
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msr = rdmsr(MTRR_PHYS_MASK(i));
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if (!(msr.lo & MTRR_PHYS_MASK_VALID))
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if (!(msr.lo & MTRR_PHYS_MASK_VALID))
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break;
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break;
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}
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}
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if (i == max_var_mtrrs)
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if (i == max_var_mtrrs)
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die("Run out of unused MTRRs\n");
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die("Run out of unused MTRRs\n");
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@ -84,7 +84,7 @@ static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt
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outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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while (cnt--) {
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while (cnt--) {
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outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
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outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
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}
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}
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/*
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/*
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#warning "Add timeout"
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#warning "Add timeout"
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@ -71,7 +71,7 @@ static void sata_init(struct device *dev)
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pci_write_config16(dev, 0x92, reg16);
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pci_write_config16(dev, 0x92, reg16);
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if (config->sata_ahci) {
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if (config->sata_ahci) {
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u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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/* Enable CR memory space decoding */
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/* Enable CR memory space decoding */
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reg16 = pci_read_config16(dev, 0x04);
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reg16 = pci_read_config16(dev, 0x04);
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@ -68,11 +68,11 @@ static void fill_in_pattrs(void)
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dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
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dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
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attrs->revid = pci_read_config8(dev, REVID);
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attrs->revid = pci_read_config8(dev, REVID);
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/* The revision to stepping IDs have two values per metal stepping. */
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/* The revision to stepping IDs have two values per metal stepping. */
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if (attrs->revid >= RID_D_STEPPING_START) {
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if (attrs->revid >= RID_D_STEPPING_START) {
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attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
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attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
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attrs->stepping += STEP_D1;
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attrs->stepping += STEP_D1;
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} else if (attrs->revid >= RID_C_STEPPING_START) {
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} else if (attrs->revid >= RID_C_STEPPING_START) {
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attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
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attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
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attrs->stepping += STEP_C0;
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attrs->stepping += STEP_C0;
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@ -828,7 +828,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
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/* 4. enable read/write test */
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/* 4. enable read/write test */
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if (wr == TE_OP_READ_CHECK) {
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if (wr == TE_OP_READ_CHECK) {
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if ((testaudpat == 1) || (testaudpat == 2)) {
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if ((testaudpat == 1) || (testaudpat == 2)) {
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/* if audio pattern, enable read only */
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/* if audio pattern, enable read only */
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/* (disable write after read), */
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/* (disable write after read), */
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/* AUDMODE=0x48[15]=0 */
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/* AUDMODE=0x48[15]=0 */
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@ -336,8 +336,8 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
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ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
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ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
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data);
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data);
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if (ret != EXYNOS_DP_SUCCESS) {
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if (ret != EXYNOS_DP_SUCCESS) {
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printk(BIOS_ERR, "DP write_to_dpcd failed\n");
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printk(BIOS_ERR, "DP write_to_dpcd failed\n");
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return -1;
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return -1;
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}
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}
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@ -467,9 +467,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
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ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
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ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
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if (ret != EXYNOS_DP_SUCCESS) {
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if (ret != EXYNOS_DP_SUCCESS) {
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printk(BIOS_ERR, "DP read lane status failed\n");
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printk(BIOS_ERR, "DP read lane status failed\n");
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edp_info->lt_info.lt_status = DP_LT_FAIL;
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edp_info->lt_info.lt_status = DP_LT_FAIL;
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return ret;
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return ret;
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}
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}
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if (lane_stat & DP_LANE_STAT_CR_DONE) {
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if (lane_stat & DP_LANE_STAT_CR_DONE) {
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