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src/{drivers,soc}: Fix some code indents 

Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Elyes HAOUAS 2022-01-27 07:55:34 +01:00 committed by Felix Held
parent f711bf03a6
commit 0bc5d9dfff
6 changed files with 11 additions and 11 deletions
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2
src/drivers/amd/agesa/mtrr_fixme.c
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@ -20,7 +20,7 @@ static void set_range_uc(u32 base, u32 size)
for (i = 0; i < max_var_mtrrs; i++) {
msr = rdmsr(MTRR_PHYS_MASK(i));
if (!(msr.lo & MTRR_PHYS_MASK_VALID))
break;
break;
}
if (i == max_var_mtrrs)
die("Run out of unused MTRRs\n");

2
src/drivers/net/ne2k.c
View File

@ -84,7 +84,7 @@ static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt
outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
while (cnt--) {
outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
}
/*
#warning "Add timeout"

2
src/soc/intel/baytrail/sata.c
View File

@ -71,7 +71,7 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x92, reg16);
if (config->sata_ahci) {
u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
/* Enable CR memory space decoding */
reg16 = pci_read_config16(dev, 0x04);

4
src/soc/intel/braswell/ramstage.c
View File

@ -68,11 +68,11 @@ static void fill_in_pattrs(void)
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_D_STEPPING_START) {
if (attrs->revid >= RID_D_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
attrs->stepping += STEP_D1;
} else if (attrs->revid >= RID_C_STEPPING_START) {
} else if (attrs->revid >= RID_C_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
attrs->stepping += STEP_C0;

2
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@ -828,7 +828,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
/* 4. enable read/write test */
if (wr == TE_OP_READ_CHECK) {
if ((testaudpat == 1) || (testaudpat == 2)) {
if ((testaudpat == 1) || (testaudpat == 2)) {
/* if audio pattern, enable read only */
/* (disable write after read), */
/* AUDMODE=0x48[15]=0 */

10
src/soc/samsung/exynos5420/dp.c
View File

@ -336,8 +336,8 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
data);
if (ret != EXYNOS_DP_SUCCESS) {
printk(BIOS_ERR, "DP write_to_dpcd failed\n");
return -1;
printk(BIOS_ERR, "DP write_to_dpcd failed\n");
return -1;
}
@ -467,9 +467,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
if (ret != EXYNOS_DP_SUCCESS) {
printk(BIOS_ERR, "DP read lane status failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret;
printk(BIOS_ERR, "DP read lane status failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret;
}
if (lane_stat & DP_LANE_STAT_CR_DONE) {