vendorcode/intel/fsp: Update MemInfoHob header for Jasper Lake
Jasper Lake has been using the incorrect MemInfoHob header. Updating the header to align it with Jasper Lake MRC code. BUG=b:158722318 TEST=Verify memory info is populated for channnel 0 and 1 on wadddledoo. Change-Id: Icca3e3b4cda9ca257f3b725823facf52ceec37b7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This commit is contained in:
Aamir Bohra
Patrick Georgi
parent
dd48b176f3
commit
0be23eda13
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@ -18,16 +18,18 @@
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#ifndef _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#pragma pack (push, 1)
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryInfoDataGuid;
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extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define MAX_TRACE_CACHE_TYPE 3
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#define MAX_NODE 1
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#define MAX_CH 2
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#define MAX_DIMM 2
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@ -43,6 +45,7 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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@ -64,8 +67,7 @@ typedef struct {
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UINT8 Build; ///< Build number
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} SiMrcVersion;
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//
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// Matches MrcChannelSts enum in MRC
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//// Matches MrcChannelSts enum in MRC
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//
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#ifndef CHANNEL_NOT_PRESENT
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#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
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@ -96,18 +98,20 @@ typedef struct {
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//
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// Matches MrcBootMode enum in MRC
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//
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#ifndef bmCold
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#define bmCold 0 // Cold boot
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#endif
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#ifndef bmWarm
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#define bmWarm 1 // Warm boot
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#endif
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#ifndef bmS3
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#define bmS3 2 // S3 resume
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#endif
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#ifndef bmFast
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#define bmFast 3 // Fast boot
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#endif
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#ifndef __MRC_BOOT_MODE__
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#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
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#ifndef INT32_MAX
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#define INT32_MAX (0x7FFFFFFF)
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#endif //INT32_MAX
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typedef enum {
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bmCold, ///< Cold boot
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bmWarm, ///< Warm boot
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bmS3, ///< S3 resume
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bmFast, ///< Fast boot
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MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
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MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
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} MRC_BOOT_MODE;
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#endif //__MRC_BOOT_MODE__
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//
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// Matches MrcDdrType enum in MRC
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@ -121,15 +125,15 @@ typedef struct {
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#ifndef MRC_DDR_TYPE_LPDDR3
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#define MRC_DDR_TYPE_LPDDR3 2
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#endif
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#ifndef CPU_CFL//CNL
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#ifndef MRC_DDR_TYPE_LPDDR4
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#define MRC_DDR_TYPE_LPDDR4 3
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#endif
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#else//CFL
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 3
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#ifndef MRC_DDR_TYPE_WIO2
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#define MRC_DDR_TYPE_WIO2 4
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 5
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#endif
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#endif//CPU_CFL-endif
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#define MAX_PROFILE_NUM 4 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
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@ -162,13 +166,6 @@ typedef struct {
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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} MRC_CH_TIMING;
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typedef struct {
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UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
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UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
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UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
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UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
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} MRC_TA_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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@ -183,7 +180,8 @@ typedef struct {
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
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UINT16 Speed; ///< The maximum capable speed of the device, in MHz
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UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
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} DIMM_INFO;
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typedef struct {
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@ -192,24 +190,24 @@ typedef struct {
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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} CONTROLLER_INFO;
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typedef struct {
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UINT64 BaseAddress; ///< Trace Base Address
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UINT64 TotalSize; ///< Total Trace Region of Same Cache type
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UINT8 CacheType; ///< Trace Cache Type
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UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
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UINT8 Rsvd[2];
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} PSMI_MEM_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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@ -251,16 +249,15 @@ typedef struct {
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT32 PrmrrBase;
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UINT64 PrmrrBase;
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UINT32 PramSize;
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UINT64 PramBase;
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UINT64 DismLimit;
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UINT64 DismBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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#ifdef CPU_CFL
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UINT32 GdxcIotBase;
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UINT32 GdxcIotSize;
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UINT32 GdxcMotBase;
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UINT32 GdxcMotSize;
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#endif //CPU_CFL
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PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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