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amd/pi/hudson: Convert 48Mhz en to read/write32 

Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marshall Dawson 2017-07-13 12:06:25 -06:00 committed by Kyösti Mälkki
parent 9e741bb218
commit 0bf3f55b5c
1 changed files with 4 additions and 5 deletions
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9
src/southbridge/amd/pi/hudson/early_setup.c
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@ -260,18 +260,17 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
void hudson_clk_output_48Mhz(void) void hudson_clk_output_48Mhz(void)
{ {
u32 data, *memptr; u32 ctrl;
/* /*
* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
* 48Mhz will be on ball AP13 (FT3b package) * 48Mhz will be on ball AP13 (FT3b package)
*/ */
memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
data = *memptr;
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
data &= (u32)~(1<<2); ctrl &= (u32)~(1<<2);
*memptr = data; write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
} }
static uintptr_t hudson_spibase(void) static uintptr_t hudson_spibase(void)