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sb/intel/bd82x6x: Add TCO_Lock in finalize step 

CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.

Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Dennis Wassenberg 2015-09-10 12:03:45 +02:00 committed by Nico Huber
parent f8960a6149
commit 0c04720cb7
2 changed files with 13 additions and 0 deletions
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10
src/southbridge/intel/bd82x6x/finalize.c
View File

@ -16,11 +16,15 @@
#include <arch/io.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
#include "pch.h"
#include <spi-generic.h>
void intel_pch_finalize_smm(void)
{
u16 tco1_cnt;
u16 pmbase;
if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) {
/* Copy flash regions from FREG0-4 to PR0-4
and enable write protection bit31 */
@ -66,6 +70,12 @@ void intel_pch_finalize_smm(void)
pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* TCO_Lock */
pmbase = smm_get_pmbase();
tco1_cnt = inw(pmbase + TCO1_CNT);
tco1_cnt |= TCO_LOCK;
outw(tco1_cnt, pmbase + TCO1_CNT);
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
}

3
src/southbridge/intel/bd82x6x/pch.h
View File

@ -534,6 +534,9 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define TCO1_STS 0x64
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
#define TCO1_CNT 0x68
#define TCO_LOCK (1 << 12)
#define TCO2_CNT 0x6a
/*
* SPI Opcode Menu setup for SPIBAR lockdown