sb/intel/bd82x6x: Add TCO_Lock in finalize step
CHIPSEC found that the TCO_Lock was not set. This is used to prevent changing the TCO_EN bit. Change-Id: I42364dbef2511e656662566cf94591e76c6847ed Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: https://review.coreboot.org/17351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -16,11 +16,15 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#include <console/post_codes.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include "pch.h"
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#include "pch.h"
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#include <spi-generic.h>
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#include <spi-generic.h>
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void intel_pch_finalize_smm(void)
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void intel_pch_finalize_smm(void)
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{
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{
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u16 tco1_cnt;
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u16 pmbase;
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if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) {
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if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) {
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/* Copy flash regions from FREG0-4 to PR0-4
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/* Copy flash regions from FREG0-4 to PR0-4
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and enable write protection bit31 */
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and enable write protection bit31 */
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@ -66,6 +70,12 @@ void intel_pch_finalize_smm(void)
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pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
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pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
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pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
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pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
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/* TCO_Lock */
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pmbase = smm_get_pmbase();
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tco1_cnt = inw(pmbase + TCO1_CNT);
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tco1_cnt |= TCO_LOCK;
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outw(tco1_cnt, pmbase + TCO1_CNT);
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/* Indicate finalize step with post code */
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/* Indicate finalize step with post code */
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outb(POST_OS_BOOT, 0x80);
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outb(POST_OS_BOOT, 0x80);
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}
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}
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@ -534,6 +534,9 @@ early_usb_init (const struct southbridge_usb_port *portmap);
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#define TCO1_STS 0x64
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define TCO2_STS 0x66
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#define TCO1_CNT 0x68
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#define TCO_LOCK (1 << 12)
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#define TCO2_CNT 0x6a
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/*
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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* SPI Opcode Menu setup for SPIBAR lockdown
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