soc/intel/adl, mb/google/brya: Add IPU to devicetree

BUG=b:181843816

Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/baseboard/devicetree.cb

@@ -91,6 +91,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		device ref igpu on end
 		device ref dtt on end
+		device ref ipu on end
 		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on end
 		device ref tbt_pcie_rp2 on end

src/soc/intel/alderlake/Kconfig

@@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_COMMON_BLOCK_MEMINIT
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_SMM

src/soc/intel/alderlake/chipset.cb

@@ -5,6 +5,7 @@ chip soc/intel/alderlake
 		device pci 01.0 alias pcie5 off end
 		device pci 02.0 alias igpu off end
 		device pci 04.0 alias dtt off end
+		device pci 05.0 alias ipu off end
 		device pci 06.0 alias pcie4_0 off end
 		device pci 06.2 alias pcie4_1 off end
 		device pci 07.0 alias tbt_pcie_rp0 off