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mb/gigabyte/ga-h61m-*: Use overridetrees 

Make use of overridetrees, as these mainboards are very similar.

Tested on GA-H61MA-D3V, still works fine.

Change-Id: I1b587a091da631cb172eb76722958da6c7518893
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39668
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-03-19 10:56:18 +01:00 committed by Patrick Georgi
parent 95cdd9f21b
commit 0c0b16ac9e
8 changed files with 215 additions and 302 deletions
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4
src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
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@ -46,9 +46,9 @@ config MAINBOARD_PART_NUMBER
default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V
default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
config DEVICETREE
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS
int

46
src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb Normal file
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@ -0,0 +1,46 @@
## SPDX-License-Identifier: GPL-2.0-only
## This file is part of the coreboot project.
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
register "pci_mmio_size" = "2048"
device domain 0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PEG
device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # MEI #1
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # HD Audio
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end

96
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb
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@ -1,96 +0,0 @@
##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
register "pci_mmio_size" = "2048"
device domain 0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PEG
device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # MEI #1
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # HD Audio
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
device pci 1c.2 off end # RP #3:
device pci 1c.3 off end # RP #4:
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2)
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM1
device pnp 2e.2 off end # COM2
device pnp 2e.3 off end # Parallel port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
io 0x62 = 0x0a20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
end
device pnp 2e.6 on end # Mouse
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x26 = 0xf7
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0x73 = 0x00
irq 0xc1 = 0x37
irq 0xcb = 0x00
irq 0xf0 = 0x10
irq 0xf1 = 0x42
irq 0xf6 = 0x1c
end
device pnp 2e.a off end # CIR
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end

52
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb Normal file
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@ -0,0 +1,52 @@
## SPDX-License-Identifier: GPL-2.0-only
## This file is part of the coreboot project.
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
device pci 1c.2 off end # RP #3:
device pci 1c.3 off end # RP #4:
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2)
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM1
device pnp 2e.2 off end # COM2
device pnp 2e.3 off end # Parallel port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
io 0x62 = 0x0a20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
end
device pnp 2e.6 on end # Mouse
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x26 = 0xf7
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0x73 = 0x00
irq 0xc1 = 0x37
irq 0xcb = 0x00
irq 0xf0 = 0x10
irq 0xf1 = 0x42
irq 0xf6 = 0x1c
end
device pnp 2e.a off end # CIR
end
end
end
end
end

104
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
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@ -1,104 +0,0 @@
##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/sandybridge
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
register "pci_mmio_size" = "2048"
device domain 0x0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16)
device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1)
device pci 1c.1 off end # RP #2:
device pci 1c.2 off end # RP #3:
device pci 1c.3 off end # RP #4:
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy, not routed.
device pnp 2e.1 on # COM1
io 0x60 = 0x03f8
irq 0x70 = 4
end
device pnp 2e.2 off end # COM2, not routed.
device pnp 2e.3 on # Parallel port
io 0x60 = 0x0378
irq 0x70 = 7
drq 0x74 = 4
end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
irq 0x70 = 9
io 0x62 = 0x0a20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
irq 0x70 = 1
io 0x62 = 0x64
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0xcb = 0x00
irq 0xf1 = 0x40
end
device pnp 2e.a off end # CIR, not routed.
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
end
end

58
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb Normal file
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@ -0,0 +1,58 @@
## SPDX-License-Identifier: GPL-2.0-only
## This file is part of the coreboot project.
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1)
device pci 1c.1 off end # RP #2:
device pci 1c.2 off end # RP #3:
device pci 1c.3 off end # RP #4:
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # COM1
io 0x60 = 0x03f8
irq 0x70 = 4
end
device pnp 2e.2 off end # COM2
device pnp 2e.3 on # Parallel port
io 0x60 = 0x0378
irq 0x70 = 7
drq 0x74 = 4
end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
irq 0x70 = 9
io 0x62 = 0x0a20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
irq 0x70 = 1
io 0x62 = 0x64
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0xcb = 0x00
irq 0xf1 = 0x40
end
device pnp 2e.a off end # CIR
end
end
end
end
end

100
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb
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@ -1,100 +0,0 @@
##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/sandybridge
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
register "pci_mmio_size" = "2048"
device domain 0x0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
device pci 1c.2 on end # RP #3: Etron EJ168 USB 3.0
device pci 1c.3 on end # RP #4: Marvell 88SE9172 SATA
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2)
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM1
device pnp 2e.2 off end # COM2
device pnp 2e.3 off end # Parallel port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
io 0x62 = 0x0a20
irq 0x70 = 9
irq 0xf2 = 0x40
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0xf0 = 0x08
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x26 = 0xf7
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0x73 = 0x00
irq 0xcb = 0x00
irq 0xf0 = 0x10
irq 0xf1 = 0x40
irq 0xf6 = 0x1c
end
device pnp 2e.a off end # CIR
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end

57
src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb Normal file
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@ -0,0 +1,57 @@
## SPDX-License-Identifier: GPL-2.0-only
## This file is part of the coreboot project.
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
device pci 1c.2 on end # RP #3: Etron EJ168 USB 3.0
device pci 1c.3 on end # RP #4: Marvell 88SE9172 SATA
device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2)
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM1
device pnp 2e.2 off end # COM2
device pnp 2e.3 off end # Parallel port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
io 0x62 = 0x0a20
irq 0x70 = 9
irq 0xf2 = 0x40
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0xf0 = 0x08
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x26 = 0xf7
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x70 = 0x00
irq 0x73 = 0x00
irq 0xcb = 0x00
irq 0xf0 = 0x10
irq 0xf1 = 0x40
irq 0xf6 = 0x1c
end
device pnp 2e.a off end # CIR
end
end
end
end
end