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rk3288: move reboot_from_watchdog() before rk808 setting 

we will use dvs to adjust the voltage in kernel, if device reset
by watchdog in kernel, the dvs gpio may not reset, and we use the
i2c to adjust rk808 voltage in coreboot, so it may failure. so we
move the reboot_from_watchdog() before the rk808 setting.

BUG=None
TEST=Boot from speedy
BRANCH=None

Change-Id: I809c63153d49680d9c84462aafd7bae09106fa6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76efb4b0196eecc84664a4c5dce2221152a39c0a
Original-Change-Id: I92b5c6413bbffe30566178de89df1f9683790982
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/244289
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
huang lin 2015-01-29 19:50:59 +08:00 committed by Patrick Georgi
parent 710e0a2726
commit 0c253b69af
4 changed files with 12 additions and 12 deletions
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6
src/mainboard/google/veyron_jerry/bootblock.c
View File

@ -45,6 +45,9 @@ void bootblock_mainboard_early_init()
void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
@ -58,9 +61,6 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
i2c_init(1, 400*KHz);

6
src/mainboard/google/veyron_mighty/bootblock.c
View File

@ -45,6 +45,9 @@ void bootblock_mainboard_early_init()
void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
@ -58,9 +61,6 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
i2c_init(1, 400*KHz);

6
src/mainboard/google/veyron_pinky/bootblock.c
View File

@ -45,6 +45,9 @@ void bootblock_mainboard_early_init()
void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
@ -58,9 +61,6 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
i2c_init(1, 400*KHz);

6
src/mainboard/google/veyron_speedy/bootblock.c
View File

@ -45,6 +45,9 @@ void bootblock_mainboard_early_init()
void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
@ -58,9 +61,6 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
i2c_init(1, 400*KHz);