diff --git a/src/soc/mediatek/mt8188/Kconfig b/src/soc/mediatek/mt8188/Kconfig
index 7a3c1e6765..193b078516 100644
--- a/src/soc/mediatek/mt8188/Kconfig
+++ b/src/soc/mediatek/mt8188/Kconfig
@@ -9,6 +9,7 @@ config SOC_MEDIATEK_MT8188
 	select SOC_MEDIATEK_COMMON
 	select FLASH_DUAL_IO_READ
 	select CACHE_MRC_SETTINGS
+	select MEDIATEK_BLOB_FAST_INIT
 
 if SOC_MEDIATEK_MT8188
 
diff --git a/src/soc/mediatek/mt8188/include/soc/dramc_param.h b/src/soc/mediatek/mt8188/include/soc/dramc_param.h
index 225872b7c3..88e2a90e61 100644
--- a/src/soc/mediatek/mt8188/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8188/include/soc/dramc_param.h
@@ -21,7 +21,70 @@
 #define DRAMC_PARAM_HEADER_VERSION 1
 
 struct sdram_params {
-	/* Not needed for full calibration */
+	/* rank, cbt */
+	u32 rank_num;
+	u32 dram_cbt_mode;
+
+	u16 delay_cell_timex100;
+	u8 u18ph_dly;
+
+	/* duty */
+	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+	s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP4 + 1];
+	s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+	s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+
+	/* cbt */
+	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
+	s16 cbt_cmd_dly[CHANNEL_MAX];
+	u16 cbt_cs_dly[CHANNEL_MAX];
+	u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
+
+	/* write leveling */
+	u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+
+	/* gating */
+	u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+
+	/* rx input buffer */
+	s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP4];
+	s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP4];
+
+	/* tx perbit */
+	u8 tx_window_vref[CHANNEL_MAX][RANK_MAX];
+	u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
+	u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+
+	/* rx datlat */
+	u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
+
+	/* rx perbit */
+	u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+	s16 rx_perbit_begin;
+
+	/* dcm */
+	u8 best_u[CHANNEL_MAX][RANK_MAX];
+	u8 best_l[CHANNEL_MAX][RANK_MAX];
+
+	/* tx oe */
+	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
+
+	/* imp k */
+	u8 sw_impedance[IMP_DRV_MAX];
 };
 
 struct dramc_data {