Revert "mb/google/reef/sand: Override USB2 phy settings"
This reverts commit aef0d6b0a7
.
This commit can only pass far-end USB eye diagram but will fail on
near-end. Confirmed with Intel we should revert it.
Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/25651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
fa529bb940
commit
0c557cd983
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@ -112,22 +112,6 @@ chip soc/intel/apollolake
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# Minimum SLP S3 assertion width 28ms.
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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register "slp_s3_assertion_width_usecs" = "28000"
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# Override USB2 PER PORT register (PORT 1)
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register "usb2eye[1]" = "{
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.Usb20PerPortPeTxiSet = 4,
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.Usb20PerPortTxiSet = 4,
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.Usb20IUsbTxEmphasisEn = 1,
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.Usb20PerPortTxPeHalf = 0,
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}"
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# Override USB2 PER PORT register (PORT 4)
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register "usb2eye[4]" = "{
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.Usb20PerPortPeTxiSet = 7,
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.Usb20PerPortTxiSet = 7,
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.Usb20IUsbTxEmphasisEn = 1,
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.Usb20PerPortTxPeHalf = 0,
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}"
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device domain 0 on
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.1 on end # - DPTF
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