GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert "mb/google/reef/sand: Override USB2 phy settings" 

This reverts commit aef0d6b0a7.

This commit can only pass far-end USB eye diagram but will fail on 
near-end. Confirmed with Intel we should revert it.

Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/25651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Katherine Hsieh 2018-04-13 06:24:51 +00:00 committed by Aaron Durbin
parent fa529bb940
commit 0c557cd983
1 changed files with 0 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/mainboard/google/reef/variants/sand/devicetree.cb
View File

@ -112,22 +112,6 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 4,
.Usb20PerPortTxiSet = 4,
.Usb20IUsbTxEmphasisEn = 1,
.Usb20PerPortTxPeHalf = 0,
}"
# Override USB2 PER PORT register (PORT 4)
register "usb2eye[4]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 7,
.Usb20IUsbTxEmphasisEn = 1,
.Usb20PerPortTxPeHalf = 0,
}"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF