diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h
index fcdcd96939..123a13fc89 100644
--- a/src/soc/amd/cezanne/include/soc/lpc.h
+++ b/src/soc/amd/cezanne/include/soc/lpc.h
@@ -3,6 +3,12 @@
 #ifndef AMD_CEZANNE_LPC_H
 #define AMD_CEZANNE_LPC_H
 
+/* LPC_MISC_CONTROL_BITS at D14F3x078 */
+/* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne
+   and newer, so we need to keep those in a SoC-specific header file. */
+#define   LPC_LDRQ0_PU_EN		BIT(10)
+#define   LPC_LDRQ0_PD_EN		BIT(9)
+
 #define SPIROM_BASE_ADDRESS_REGISTER	0xa0
 #define   SPI_BASE_ALIGNMENT		BIT(8)
 #define   SPI_BASE_RESERVED		(BIT(5) | BIT(6) | BIT(7))
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index aa483e4df7..daa51f1145 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -105,6 +105,8 @@
 #define   LPC_ALT_WIDEIO0_ENABLE	BIT(0)
 
 #define LPC_MISC_CONTROL_BITS		0x78
+#define   LPC_LDRQ1_EN			BIT(3)
+#define   LPC_LDRQ0_EN			BIT(2)
 #define   LPC_NOHOG			BIT(0)
 
 #define LPC_TRUSTED_PLATFORM_MODULE	0x7c