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soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region 

Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
As x86 systems preserves the upper 16 MiB below 4G for BIOS flash
decoding use the complete window for reporting independent of the
actually used SPI flash size. This will block the preserved MMIO window.

Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Werner Zeh 2022-05-05 14:56:07 +02:00 committed by Felix Held
parent 79df32d083
commit 0c78f4c05a
1 changed files with 14 additions and 1 deletions
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15
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -22,6 +22,9 @@
#include <spi_flash.h>
#include <spi-generic.h>
#define FLASH_MMIO_SIZE (16 * MiB)
#define FLASH_BASE_ADDR ((0xffffffff - FLASH_MMIO_SIZE) + 1)
/*
* Get the FAST_SPIBAR.
*/
@ -514,8 +517,18 @@ static void fast_spi_fill_ssdt(const struct device *dev)
acpigen_pop_len(); /* Scope */
}
static void fast_spi_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
/* Add SPI flash MMIO window as a reserved resource. */
mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, FLASH_MMIO_SIZE / KiB);
}
static struct device_operations fast_spi_dev_ops = {
.read_resources = pci_dev_read_resources,
.read_resources = fast_spi_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt = fast_spi_fill_ssdt,