From 0c7a25069e0d855013d082a87b5810c60336acb9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 13:53:15 +0200 Subject: [PATCH] soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 821694eb53..99fcadd581 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -62,8 +62,9 @@ static void configure_c_states(const config_t *const cfg) msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } + msr.lo |= CST_CFG_LOCK_MASK; + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0;