nb/intel/{i945,sandybridge}/bootblock.c: Fix typo
Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38245 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -26,7 +26,7 @@ void bootblock_early_northbridge_init(void)
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
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* CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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*
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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* 4GiB.
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@ -26,7 +26,7 @@ void bootblock_early_northbridge_init(void)
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
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* CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
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*
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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* 4GiB.
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