drivers/analogix/anx7625: Fix edid_read()
The current implementations of edid_read() and segments_edid_read() have a few problems: 1. The type of variable `c` is incorrect, not matching the return type of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown. 2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails. 3. These two functions ignore the return value of anx7625_reg_block_read(). 4. In segments_edid_read(), anx7625_reg_write() might return a positive value on failure. Fix all of the 4 issues, and modify the code to be closer to kernel 5.10's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note that, however, unlike in kernel, anx7625_reg_block_read() here doesn't return the number of bytes. On success, 0 is returned instead. In addition, following coreboot's convention, always return negative error codes. In particular, change the return value to -1 for edid_read() and segments_edid_read() on failure. BUG=b:207055969 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yu-Ping Wu
Hung-Te Lin
parent
74033df2bd
commit
0c9b1deb63
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@ -54,10 +54,12 @@ static int i2c_access_workaround(uint8_t bus, uint8_t saddr)
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}
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ret = i2c_writeb(bus, saddr, offset, 0x00);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("Failed to access %#x:%#x\n", saddr, offset);
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return ret;
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}
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return 0;
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}
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static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset,
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uint8_t *val)
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@ -70,7 +72,7 @@ static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset,
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ANXERROR("Failed to read i2c reg=%#x:%#x\n", saddr, offset);
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return ret;
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}
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return *val;
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return 0;
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}
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static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
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@ -80,11 +82,13 @@ static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
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i2c_access_workaround(bus, saddr);
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ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x]\n", saddr,
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reg_addr, len);
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return ret;
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}
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return 0;
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}
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static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
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uint8_t reg_val)
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@ -93,11 +97,12 @@ static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
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i2c_access_workaround(bus, saddr);
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ret = i2c_writeb(bus, saddr, reg_addr, reg_val);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("Failed to write i2c id=%#x:%#x\n", saddr, reg_addr);
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return ret;
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}
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return 0;
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}
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static int anx7625_write_or(uint8_t bus, uint8_t saddr, uint8_t offset,
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uint8_t mask)
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@ -128,30 +133,31 @@ static int anx7625_write_and(uint8_t bus, uint8_t saddr, uint8_t offset,
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static int wait_aux_op_finish(uint8_t bus)
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{
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uint8_t val;
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int ret = -1;
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int loop;
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int success = 0;
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int ret;
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for (loop = 0; loop < 150; loop++) {
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mdelay(2);
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anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val);
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if (!(val & AP_AUX_CTRL_OP_EN)) {
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ret = 0;
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success = 1;
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break;
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}
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}
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if (ret != 0) {
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if (!success) {
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ANXERROR("Timed out waiting aux operation.\n");
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return ret;
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return -1;
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}
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ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val);
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if (ret < 0 || val & 0x0F) {
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ANXDEBUG("aux status %02x\n", val);
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ret = -1;
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return -1;
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}
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return ret;
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return 0;
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}
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static unsigned long gcd(unsigned long a, unsigned long b)
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@ -210,7 +216,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
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ANXERROR("pixelclock %u higher than %lu, "
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"output may be unstable\n",
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pixelclock, PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
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return 1;
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return -1;
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}
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if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
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@ -218,7 +224,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
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ANXERROR("pixelclock %u lower than %lu, "
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"output may be unstable\n",
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pixelclock, PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
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return 1;
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return -1;
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}
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post_divider = 1;
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@ -237,7 +243,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
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if (post_divider > POST_DIVIDER_MAX) {
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ANXERROR("cannot find property post_divider(%d)\n",
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post_divider);
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return 1;
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return -1;
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}
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}
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@ -256,7 +262,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
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if (pixelclock * post_divider > PLL_OUT_FREQ_ABS_MAX) {
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ANXINFO("act clock(%u) large than maximum(%lu)\n",
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pixelclock * post_divider, PLL_OUT_FREQ_ABS_MAX);
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return 1;
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return -1;
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}
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*m = pixelclock;
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@ -292,12 +298,14 @@ static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider)
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ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7,
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MIPI_PLL_RESET_N);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("IO error.\n");
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return ret;
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}
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return 0;
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}
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static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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{
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unsigned long m, n;
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@ -305,10 +313,8 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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int ret;
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uint8_t post_divider = 0;
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ret = anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n,
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&post_divider);
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if (ret != 0) {
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if (anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n,
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&post_divider) < 0) {
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ANXERROR("cannot get property m n value.\n");
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return -1;
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}
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@ -385,12 +391,14 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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ret |= anx7625_odfc_config(bus, post_divider - 1);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("mipi dsi setup IO error.\n");
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return ret;
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}
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return 0;
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}
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static int anx7625_swap_dsi_lane3(uint8_t bus)
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{
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int ret;
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@ -400,7 +408,7 @@ static int anx7625_swap_dsi_lane3(uint8_t bus)
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ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val);
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if (ret < 0) {
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ANXERROR("IO error: access MIPI_SWAP.\n");
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return -1;
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return ret;
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}
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val |= (1 << MIPI_SWAP_CH3);
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@ -461,12 +469,14 @@ static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt)
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ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x00);
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ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x80);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("IO error: mipi dsi enable init failed.\n");
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return ret;
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}
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return 0;
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}
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static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt)
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{
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int ret;
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@ -487,14 +497,15 @@ static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt)
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/* clear mute flag */
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ret |= anx7625_write_and(bus, RX_P0_ADDR, AP_AV_STATUS, ~AP_MIPI_MUTE);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("IO error: enable mipi rx failed.\n");
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else
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ANXINFO("success to config DSI\n");
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return ret;
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}
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ANXINFO("success to config DSI\n");
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return 0;
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}
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static int sp_tx_rst_aux(uint8_t bus)
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{
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int ret;
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@ -549,34 +560,32 @@ static int sp_tx_get_edid_block(uint8_t bus)
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static int edid_read(uint8_t bus, uint8_t offset, uint8_t *pblock_buf)
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{
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uint8_t c, cnt = 0;
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int ret, cnt;
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c = 0;
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for (cnt = 0; cnt < 3; cnt++) {
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sp_tx_aux_wr(bus, offset);
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/* set I2C read com 0x01 mot = 0 and read 16 bytes */
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c = sp_tx_aux_rd(bus, 0xf1);
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ret = sp_tx_aux_rd(bus, 0xf1);
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if (c == 1) {
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if (ret < 0) {
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sp_tx_rst_aux(bus);
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ANXERROR("edid read failed, reset!\n");
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cnt++;
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} else {
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anx7625_reg_block_read(bus, RX_P0_ADDR,
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if (anx7625_reg_block_read(bus, RX_P0_ADDR,
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AP_AUX_BUFF_START,
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MAX_DPCD_BUFFER_SIZE, pblock_buf);
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MAX_DPCD_BUFFER_SIZE,
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pblock_buf) >= 0)
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return 0;
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}
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}
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return 1;
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return -1;
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}
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static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf,
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uint8_t offset)
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{
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uint8_t c, cnt = 0;
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int ret;
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int ret, cnt;
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/* write address only */
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ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x30);
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@ -598,21 +607,21 @@ static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf,
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for (cnt = 0; cnt < 3; cnt++) {
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sp_tx_aux_wr(bus, offset);
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/* set I2C read com 0x01 mot = 0 and read 16 bytes */
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c = sp_tx_aux_rd(bus, 0xf1);
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ret = sp_tx_aux_rd(bus, 0xf1);
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if (c == 1) {
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ret = sp_tx_rst_aux(bus);
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if (ret < 0) {
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sp_tx_rst_aux(bus);
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ANXERROR("segment read failed, reset!\n");
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cnt++;
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} else {
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ret = anx7625_reg_block_read(bus, RX_P0_ADDR,
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if (anx7625_reg_block_read(bus, RX_P0_ADDR,
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AP_AUX_BUFF_START,
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MAX_DPCD_BUFFER_SIZE, buf);
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return ret;
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MAX_DPCD_BUFFER_SIZE,
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buf) >= 0)
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return 0;
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}
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}
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return ret;
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return -1;
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}
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static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
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@ -621,9 +630,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
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uint8_t offset, edid_pos;
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int count, blocks_num;
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uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE];
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uint8_t i;
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uint8_t g_edid_break = 0;
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int ret;
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int i, ret, g_edid_break = 0;
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/* address initial */
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ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50);
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@ -637,7 +644,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
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blocks_num = sp_tx_get_edid_block(bus);
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if (blocks_num < 0)
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return blocks_num;
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return -1;
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count = 0;
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@ -647,10 +654,10 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
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case 1:
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for (i = 0; i < 8; i++) {
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offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
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g_edid_break = edid_read(bus, offset,
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g_edid_break = !!edid_read(bus, offset,
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pblock_buf);
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if (g_edid_break == 1)
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if (g_edid_break)
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break;
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if (offset <= size - MAX_DPCD_BUFFER_SIZE)
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@ -668,7 +675,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
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edid_pos = (i + count * 8) *
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MAX_DPCD_BUFFER_SIZE;
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if (g_edid_break == 1)
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if (g_edid_break)
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break;
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segments_edid_read(bus, count / 2,
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@ -834,14 +841,15 @@ int anx7625_dp_start(uint8_t bus, const struct edid *edid)
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anx7625_parse_edid(edid, &dt);
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ret = anx7625_dsi_config(bus, &dt);
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if (ret < 0)
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if (ret < 0) {
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ANXERROR("MIPI phy setup error.\n");
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else
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ANXINFO("MIPI phy setup OK.\n");
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return ret;
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}
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ANXINFO("MIPI phy setup OK.\n");
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return 0;
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}
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int anx7625_dp_get_edid(uint8_t bus, struct edid *out)
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{
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int block_num;
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@ -869,7 +877,7 @@ int anx7625_init(uint8_t bus)
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int retry_power_on = 3;
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while (--retry_power_on) {
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if (anx7625_power_on_init(bus) == 0)
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if (anx7625_power_on_init(bus) >= 0)
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break;
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}
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if (!retry_power_on) {
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