IEI PM-LX-800-R11: Added preliminary mainboard support
Details for this board are available at http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110 Most of the functionality provided by the original BIOS is implemented. Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715 Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1168 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
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0ca02553e1
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@ -29,6 +29,8 @@ config BOARD_IEI_NOVA_4899R
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bool "NOVA-4899R"
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config BOARD_IEI_PCISA_LX_800_R10
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bool "PCISA LX-800-R10"
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config BOARD_IEI_PM_LX_800_R11
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bool "PM LX-800-R11"
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endchoice
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@ -36,6 +38,7 @@ source "src/mainboard/iei/juki-511p/Kconfig"
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source "src/mainboard/iei/kino-780am2-fam10/Kconfig"
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source "src/mainboard/iei/nova4899r/Kconfig"
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source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig"
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source "src/mainboard/iei/pm-lx-800-r11/Kconfig"
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config MAINBOARD_VENDOR
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string
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@ -0,0 +1,67 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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if BOARD_IEI_PM_LX_800_R11
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_AMD_GEODE_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select SUPERIO_WINBOND_W83627EHG
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select BOARD_ROMSIZE_KB_512
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select POWER_BUTTON_FORCE_ENABLE
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config MAINBOARD_DIR
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string
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default iei/pm-lx-800-r11
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config MAINBOARD_PART_NUMBER
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string
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default "PM-LX-800-R11"
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config IRQ_SLOT_COUNT
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int
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default 7
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choice
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prompt "Core/GLIU Frequency"
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default CORE_GLIU_500_266
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config CORE_GLIU_500_266
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bool "500MHz / 266MHz"
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config CORE_GLIU_500_333
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bool "500MHz / 333MHz"
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config CORE_GLIU_500_400
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bool "500MHz / 400MHz"
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endchoice
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config CORE_GLIU
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int
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default 7
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endif # BOARD_IEI_PM_LX_800_R11
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,101 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Video Adapter
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device pci 1.2 on end # AES Security Block
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chip southbridge/amd/cs5536
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register "lpc_serirq_enable" = "0x0000115a"
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register "lpc_serirq_polarity" = "0x0000eea5"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0d0c0700"
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register "enable_ide_nand_flash" = "0"
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register "enable_USBP4_device" = "0" # 0:host, 1:device
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register "enable_USBP4_overcurrent" = "0"
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register "com1_enable" = "1" # CN10 (RS422/486 COM3)
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register "com1_address" = "0x3e8"
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register "com1_irq" = "5"
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register "com2_enable" = "0"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci e.0 on end # RTL8100C
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device pci f.0 on # ISA Bridge
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chip superio/winbond/w83627ehg # Winbond W83627EHG
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # PS/2 keyboard/mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # Keyboard
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irq 0x72 = 12 # Mouse
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end
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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device pnp 2e.6 off end # Serial Flash Interface
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device pnp 2e.7 off end # GPIO1, GPIO6, Game Port & MIDI Port
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device pnp 2e.8 off end # WDTO# & PLED
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device pnp 2e.9 off end # GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED
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device pnp 2e.a off end # ACPI
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device pnp 2e.106 off end #
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device pnp 2e.107 off end #
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device pnp 2e.207 off end #
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end
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end
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device pci f.2 on end # IDE Controller
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device pci f.3 off end # Audio (N/A)
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,228 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/pci_ids.h>
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#include <arch/pirq_routing.h>
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/* Platform IRQs */
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#define PIRQA 10
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#define PIRQB 11
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#define PIRQC 11
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#define PIRQD 11
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/* Links */
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#define L_PIRQA 1
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#define L_PIRQB 2
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#define L_PIRQC 3
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#define L_PIRQD 4
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/* Bitmaps */
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#define B_LINK0 (1 << PIRQA)
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#define B_LINK1 (1 << PIRQB)
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#define B_LINK2 (1 << PIRQC)
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#define B_LINK3 (1 << PIRQD)
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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0x0f << 3, /* Interrupt router dev */
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B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3, /* IRQs devoted exclusively to PCI usage */
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PCI_VENDOR_ID_AMD, /* Vendor */
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PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
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0, /* Miniport */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* Reserved */
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0xa6, /* Checksum */
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{
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[0] = { /* Host bridge */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x01 << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[1] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[2] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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},
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[3] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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}
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}
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},
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[1] = { /* ISA bridge */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x0f << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[1] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[2] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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},
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[3] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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}
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}
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},
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[2] = { /* Ethernet */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x0e << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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},
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[1] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[2] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[3] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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}
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}
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},
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[3] = { /* PCI Connector - Slot 0 */
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.slot = 0x01,
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.bus = 0x00,
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.devfn = (0x09 << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[1] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[2] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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},
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[3] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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}
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}
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},
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[4] = { /* PCI Connector - Slot 1 */
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.slot = 0x02,
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.bus = 0x00,
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.devfn = (0x0c << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[1] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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},
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[2] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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},
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[3] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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}
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}
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},
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[5] = { /* PCI Connector - Slot 2 */
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.slot = 0x03,
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.bus = 0x00,
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.devfn = (0x0b << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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},
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[1] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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},
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[2] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[3] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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}
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}
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},
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[6] = { /* PCI Connector - Slot 3 */
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.slot = 0x04,
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.bus = 0x00,
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.devfn = (0x0a << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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},
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[1] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[2] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[3] = {
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.link = L_PIRQC,
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.bitmap = B_LINK2
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}
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}
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}
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}
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||||
};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,25 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
struct chip_operations mainboard_ops = {
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CHIP_NAME("IEI PM-LX-800-R11 Mainboard")
|
||||
};
|
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@ -0,0 +1,88 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <spd.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <arch/llshell.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
#include <southbridge/amd/cs5536/early_smbus.c>
|
||||
#include <southbridge/amd/cs5536/early_setup.c>
|
||||
#include <superio/winbond/w83627ehg/early_serial.c>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
|
||||
|
||||
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
/* Only DIMM0 is available. */
|
||||
if (device != DIMM0)
|
||||
return 0xff;
|
||||
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#if CONFIG_CORE_GLIU_500_400
|
||||
# define PLLMSRhi 0x0000059c
|
||||
#elif CONFIG_CORE_GLIU_500_333
|
||||
# define PLLMSRhi 0x0000049c
|
||||
#else
|
||||
# define PLLMSRhi 0x0000039c
|
||||
#endif
|
||||
|
||||
#define PLLMSRlo 0x07de000
|
||||
|
||||
#include <northbridge/amd/lx/raminit.h>
|
||||
#include <northbridge/amd/lx/pll_reset.c>
|
||||
#include <northbridge/amd/lx/raminit.c>
|
||||
#include <lib/generic_sdram.c>
|
||||
#include <cpu/amd/geode_lx/cpureginit.c>
|
||||
#include <cpu/amd/geode_lx/syspreinit.c>
|
||||
#include <cpu/amd/geode_lx/msrinit.c>
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {DIMM0, DIMM1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
report_bist_failure(bist);
|
||||
|
||||
pll_reset(1);
|
||||
|
||||
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
}
|
Loading…
Reference in New Issue