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amd/stoneyridge: Clear SMI_EVENT_STATUS when entering S3/S5 

disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused
us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then
wake early from sleep when waiting for a cr50 reset to turn on a cr50
update.

BUG=b:121203745
TEST=Careena remains in S5 until cr50 reset after cr50 update, and
ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog.

Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Edward Hill 2018-12-18 20:19:36 -07:00 committed by Martin Roth
parent d652a92a6a
commit 0ca3a0792d
1 changed files with 1 additions and 0 deletions
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1
src/soc/amd/stoneyridge/smihandler.c
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@ -113,6 +113,7 @@ static void sb_apmc_smi_handler(void)
static void disable_all_smi_status(void) static void disable_all_smi_status(void)
{ {
smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS));
smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS));
smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0));
smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1));
smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2));