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bd82x6x boards: Drop redundant `c2_latency` 

If unspecified, chipset code already uses 101, and 0x65 == 101.

Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2021-06-04 11:18:39 +02:00 committed by Werner Zeh
parent d4e68eb414
commit 0caf80d8aa
31 changed files with 0 additions and 37 deletions
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1
src/mainboard/apple/macbookair4_2/devicetree.cb
View File

@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
device domain 0 on device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
register "gen1_dec" = "0x000c0681" register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641" register "gen2_dec" = "0x000c1641"

1
src/mainboard/asrock/b75pro3-m/devicetree.cb
View File

@ -33,7 +33,6 @@ chip northbridge/intel/sandybridge
subsystemid 0x1849 0x0152 subsystemid 0x1849 0x0152
end end
chip southbridge/intel/bd82x6x chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291" register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0241" register "gen2_dec" = "0x000c0241"

1
src/mainboard/asus/h61-series/devicetree.cb
View File

@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # iGPU device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

1
src/mainboard/asus/maximus_iv_gene-z/devicetree.cb
View File

@ -19,7 +19,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # VGA controller device pci 02.0 on end # VGA controller
chip southbridge/intel/bd82x6x chip southbridge/intel/bd82x6x
register "c2_latency" = "101"
register "gen1_dec" = "0x00000295" # Super I/O HWM register "gen1_dec" = "0x00000295" # Super I/O HWM
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/asus/p8z77-series/devicetree.cb
View File

@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # iGPU device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/biostar/th61-itx/devicetree.cb
View File

@ -18,7 +18,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # iGPU device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01" register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"

1
src/mainboard/compulab/intense_pc/devicetree.cb
View File

@ -31,7 +31,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx
subsystemid 0x8086 0x7270 inherit subsystemid 0x8086 0x7270 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1" register "docking_supported" = "1"
register "gen1_dec" = "0x0000164d" register "gen1_dec" = "0x0000164d"
register "gen2_dec" = "0x000c0681" register "gen2_dec" = "0x000c0681"

1
src/mainboard/dell/optiplex_9010/devicetree.cb
View File

@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge
register "alt_gp_smi_en" = "0x0004" register "alt_gp_smi_en" = "0x0004"
register "gpi2_routing" = "1" register "gpi2_routing" = "1"
register "gpi12_routing" = "2" register "gpi12_routing" = "2"
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x007c0a01" register "gen1_dec" = "0x007c0a01"
register "gen2_dec" = "0x007c0901" register "gen2_dec" = "0x007c0901"
register "gen3_dec" = "0x003c07e1" register "gen3_dec" = "0x003c07e1"

1
src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
View File

@ -31,7 +31,6 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0xf" register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf" register "superspeed_capable_ports" = "0xf"
register "c2_latency" = "0x0065"
device pci 14.0 on # USB 3.0 Controller device pci 14.0 on # USB 3.0 Controller
subsystemid 0x1458 0x5007 subsystemid 0x1458 0x5007

1
src/mainboard/gigabyte/ga-h61m-series/devicetree.cb
View File

@ -18,7 +18,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # iGPU device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01" register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"

2
src/mainboard/google/butterfly/devicetree.cb
View File

@ -60,8 +60,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
device pci 14.0 on end # USB 3.0 Controller device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
View File

@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
register "gen1_dec" = "0x00fc0601" register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0801"

1
src/mainboard/hp/snb_ivb_laptops/devicetree.cb
View File

@ -29,7 +29,6 @@ chip northbridge/intel/sandybridge
device pci 00.0 on end # Host bridge device pci 00.0 on end # Host bridge
chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH
register "c2_latency" = "0x0065"
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

1
src/mainboard/hp/z220_sff_workstation/devicetree.cb
View File

@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 7 PCH chip southbridge/intel/bd82x6x # Intel Series 7 PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
register "gen1_dec" = "0x00fc0601" register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0801"

1
src/mainboard/intel/dcp847ske/devicetree.cb
View File

@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "sata_port_map" = "0x1" register "sata_port_map" = "0x1"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

2
src/mainboard/kontron/ktqm77/devicetree.cb
View File

@ -34,8 +34,6 @@ chip northbridge/intel/sandybridge
# Disable root port coalescing # Disable root port coalescing
register "pcie_port_coalesce" = "0" register "pcie_port_coalesce" = "0"
register "c2_latency" = "101" # c2 not supported
register "xhci_switchable_ports" = "0x0f" register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f"

1
src/mainboard/lenovo/l520/devicetree.cb
View File

@ -30,7 +30,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1" register "docking_supported" = "1"
register "gen1_dec" = "0x007c1611" register "gen1_dec" = "0x007c1611"
register "gen2_dec" = "0x00040069" register "gen2_dec" = "0x00040069"

1
src/mainboard/lenovo/s230u/devicetree.cb
View File

@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # Internal graphics VGA controller device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1" register "docking_supported" = "1"
register "gen1_dec" = "0x00000000" register "gen1_dec" = "0x00000000"
register "gen2_dec" = "0x000c0701" register "gen2_dec" = "0x000c0701"

2
src/mainboard/lenovo/t420/devicetree.cb
View File

@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
# device specific SPI configuration # device specific SPI configuration
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

2
src/mainboard/lenovo/t420s/devicetree.cb
View File

@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
# device specific SPI configuration # device specific SPI configuration
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/t430/devicetree.cb
View File

@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge
subsystemid 0x17aa 0x21f3 inherit subsystemid 0x17aa 0x21f3 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1" register "docking_supported" = "1"
register "gen1_dec" = "0x000c15e1" register "gen1_dec" = "0x000c15e1"
register "gen2_dec" = "0x007c1601" register "gen2_dec" = "0x007c1601"

1
src/mainboard/lenovo/t430s/devicetree.cb
View File

@ -59,7 +59,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "docking_supported" = "1" register "docking_supported" = "1"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

2
src/mainboard/lenovo/t520/devicetree.cb
View File

@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

1
src/mainboard/lenovo/t530/devicetree.cb
View File

@ -53,7 +53,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"

1
src/mainboard/lenovo/x131e/devicetree.cb
View File

@ -56,7 +56,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "0x0065"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
View File

@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

2
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -59,7 +59,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"

1
src/mainboard/msi/ms7707/devicetree.cb
View File

@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 off end # Internal graphics device pci 02.0 off end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291" register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01" register "gen2_dec" = "0x000c0a01"

1
src/mainboard/sapphire/pureplatinumh61/devicetree.cb
View File

@ -12,7 +12,6 @@ chip northbridge/intel/sandybridge
end end
device domain 0 on device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291" register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01" register "gen2_dec" = "0x000c0a01"
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"

1
src/mainboard/supermicro/x9scl/devicetree.cb
View File

@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 off end # iGPU device pci 02.0 off end # iGPU
device pci 06.0 on end # PEG device pci 06.0 on end # PEG
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff)
register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3)