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samsung/lumpy,stumpy: Refactor ChromeOS GPIOs 

Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-11-06 20:51:58 +02:00
parent 6de8b42482
commit 0cb116647e
4 changed files with 45 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/samsung/lumpy/chromeos.c
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@ -9,9 +9,7 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <types.h> #include <types.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
#define FLAG_SPI_WP 0 #define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1 #define FLAG_REC_MODE 1
@ -42,6 +40,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
static bool raw_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
}
static bool raw_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
}
int get_write_protect_state(void) int get_write_protect_state(void)
{ {
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@ -60,10 +68,10 @@ void init_bootmode_straps(void)
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
if (get_gpio(GPIO_SPI_WP)) if (raw_write_protect_state())
flags |= (1 << FLAG_SPI_WP); flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE)) if (raw_recovery_mode_switch())
flags |= (1 << FLAG_REC_MODE); flags |= (1 << FLAG_REC_MODE);
pci_s_write_config32(dev, SATA_SP, flags); pci_s_write_config32(dev, SATA_SP, flags);

6
src/mainboard/samsung/lumpy/onboard.h
View File

@ -12,4 +12,10 @@
#define BOARD_TRACKPAD_IRQ 21 #define BOARD_TRACKPAD_IRQ 21
#define BOARD_TRACKPAD_WAKE_GPIO 0x1b #define BOARD_TRACKPAD_WAKE_GPIO 0x1b
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
#define GPIO_SPI_WP 24
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
#define GPIO_REC_MODE 42
#endif #endif

19
src/mainboard/samsung/stumpy/chromeos.c
View File

@ -8,9 +8,7 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <types.h> #include <types.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
#define FLAG_SPI_WP 0 #define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1 #define FLAG_REC_MODE 1
@ -38,6 +36,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
static bool raw_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
}
static bool raw_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
}
int get_write_protect_state(void) int get_write_protect_state(void)
{ {
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@ -56,10 +64,11 @@ void init_bootmode_straps(void)
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP)) if (raw_write_protect_state())
flags |= (1 << FLAG_SPI_WP); flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE)) if (raw_recovery_mode_switch())
flags |= (1 << FLAG_REC_MODE); flags |= (1 << FLAG_REC_MODE);
pci_s_write_config32(dev, SATA_SP, flags); pci_s_write_config32(dev, SATA_SP, flags);

12
src/mainboard/samsung/stumpy/onboard.h Normal file
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@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef STUMPY_ONBOARD_H
#define STUMPY_ONBOARD_H
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
#define GPIO_REC_MODE 42
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
#define GPIO_SPI_WP 68
#endif