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arch/x86: Clean up CONFIG_SMP and MAX_CPUS test 

Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-08-18 11:46:32 +03:00
parent ff284f6566
commit 0cc2ce4327
8 changed files with 31 additions and 40 deletions
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4
src/cpu/intel/fsp_model_206ax/model_206ax_init.c
View File

@ -316,14 +316,12 @@ static void intel_cores_init(struct device *cpu)
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* Start the new CPU */
if (!start_cpu(new)) {
if (is_smp_boot() && !start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
#endif
}
}

4
src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View File

@ -115,14 +115,12 @@ static void intel_cores_init(struct device *cpu)
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* Start the new CPU */
if (!start_cpu(new)) {
if (is_smp_boot() && !start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
#endif
}
}

4
src/cpu/intel/model_2065x/model_2065x_init.c
View File

@ -295,14 +295,12 @@ static void intel_cores_init(struct device *cpu)
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* Start the new CPU */
if (!start_cpu(new)) {
if (is_smp_boot() && !start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
#endif
}
}

4
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@ -489,14 +489,12 @@ static void intel_cores_init(struct device *cpu)
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* Start the new CPU */
if (!start_cpu(new)) {
if (is_smp_boot() && !start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
#endif
}
}

2
src/cpu/x86/lapic/Makefile.inc
View File

@ -1,6 +1,6 @@
ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
ramstage-$(CONFIG_SMP) += secondary.S
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c

46
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -36,7 +36,6 @@
#include <cpu/intel/speedstep.h>
#include <thread.h>
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@ -255,7 +254,7 @@ static atomic_t active_cpus = ATOMIC_INIT(1);
* start_cpu returns.
*/
static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
DECLARE_SPIN_LOCK(start_cpu_lock);
static unsigned int last_cpu_index = 0;
static void *stacks[CONFIG_MAX_CPUS];
volatile unsigned long secondary_stack;
@ -527,12 +526,10 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
}
printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
checkstack(_estack, 0);
for (i = 1; i <= last_cpu_index; i++)
for (i = 1; i < CONFIG_MAX_CPUS && i <= last_cpu_index; i++)
checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i);
}
#endif /* CONFIG_SMP */
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
@ -557,45 +554,44 @@ void initialize_cpus(struct bus *cpu_bus)
/* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
// why here? In case some day we can start core1 in amd_sibling_init
copy_secondary_start_to_lowest_1M();
#endif
if (is_smp_boot())
copy_secondary_start_to_lowest_1M();
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
smm_init();
#endif
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* start all aps at first, so we can init ECC all together */
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
#endif
/* Initialize the bootstrap processor */
cpu_initialize(0);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) {
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);
#endif
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);
}
if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
smm_init();
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
#endif
if (is_smp_boot()) {
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
}
}
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
recover_lowest_1M();
#endif
if (is_smp_boot())
recover_lowest_1M();
}
/* Platform-specific code for SMI handler overrides this. */
__attribute__((weak)) void smm_init(void)
{
}

2
src/cpu/x86/lapic/secondary.S
View File

@ -14,7 +14,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
.text
.globl _secondary_start, _secondary_start_end, _secondary_gdt_addr
.balign 4096
@ -80,4 +79,3 @@ __ap_protected_start:
jmp 1b
.code32
#endif

5
src/include/smp/node.h
View File

@ -7,4 +7,9 @@ int boot_cpu(void);
#define boot_cpu(x) 1
#endif
static inline int is_smp_boot(void)
{
return IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1;
}
#endif /* _SMP_NODE_H_ */