GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

inteltool: Add support for Sandy Bridge desktop processors 

Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>
This commit is contained in:
Felix Held 2014-11-05 03:18:44 +01:00 committed by Mathias Krause
parent 5e1d34b19a
commit 0cc8f29316
4 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
util/inteltool/inteltool.c
View File

@ -73,7 +73,8 @@ static const struct {
/* Host bridges /DRAM controllers integrated in CPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, "2nd generation (Sandy Bridge family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M, "2nd generation (Sandy Bridge family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A, "3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B, "3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C, "3rd generation (Ivy Bridge family) Core Processor" },

3
util/inteltool/inteltool.h
View File

@ -155,7 +155,8 @@
/* Intel starts counting these generations with the integration of the DRAM controller */
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A 0x0150 /* Ivy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B 0x0154 /* Ivy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */

6
util/inteltool/memory.c
View File

@ -205,7 +205,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
@ -251,7 +252,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
ivybridge_dump_timings();
break;
}

3
util/inteltool/pcie.c
View File

@ -294,7 +294,8 @@ int print_dmibar(struct pci_dev *nb)
dmi_registers = westmere_dmi_registers;
size = ARRAY_SIZE(westmere_dmi_registers);
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
dmi_registers = sandybridge_dmi_registers;
size = ARRAY_SIZE(sandybridge_dmi_registers);
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */