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vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc 

CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.

Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.

The CPX-SP soc code is updated accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This commit is contained in:
Jonathan Zhang 2020-07-08 14:26:55 -07:00 committed by Patrick Georgi
parent bb50c67227
commit 0ccb3828bc
5 changed files with 101 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/intel/xeon_sp/cpx/hob_display.c
View File

@ -142,14 +142,14 @@ void soc_display_iio_universal_data_hob(void)
hob->PlatformData.IIO_resource[s].IoApicBase); hob->PlatformData.IIO_resource[s].IoApicBase);
printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
hob->PlatformData.IIO_resource[s].IoApicLimit); hob->PlatformData.IIO_resource[s].IoApicLimit);
printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", printk(BIOS_DEBUG, "\tMmio32Base: 0x%x\n",
hob->PlatformData.IIO_resource[s].PciResourceMem32Base); hob->PlatformData.IIO_resource[s].Mmio32Base);
printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", printk(BIOS_DEBUG, "\tMmio32Limit: 0x%x\n",
hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); hob->PlatformData.IIO_resource[s].Mmio32Limit);
printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", printk(BIOS_DEBUG, "\tMmio64Base: 0x%llx\n",
hob->PlatformData.IIO_resource[s].PciResourceMem64Base); hob->PlatformData.IIO_resource[s].Mmio64Base);
printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", printk(BIOS_DEBUG, "\tMmio64Limit: 0x%llx\n",
hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); hob->PlatformData.IIO_resource[s].Mmio64Limit);
printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
@ -158,12 +158,22 @@ void soc_display_iio_universal_data_hob(void)
printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality); printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality);
printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase);
printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit);
printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base);
printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit);
printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base);
printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit);
printk(BIOS_DEBUG, "\t\tPciResourceBusBase: 0x%x\n",
ri->PciResourceBusBase);
printk(BIOS_DEBUG, "\t\tPciResourceBusLimit: 0x%x\n",
ri->PciResourceBusLimit);
printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
ri->PciResourceIoBase); ri->PciResourceIoBase);
printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
ri->PciResourceIoLimit); ri->PciResourceIoLimit);
printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
ri->PciResourceMem32Base); ri->PciResourceMem32Base);
printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",

2
src/soc/intel/xeon_sp/cpx/romstage.c
View File

@ -12,7 +12,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
/* /*

4
src/soc/intel/xeon_sp/cpx/upd_display.c
View File

@ -12,8 +12,8 @@ void soc_display_fspm_upd_params(
const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd) const FSPM_UPD *fspm_new_upd)
{ {
const FSP_M_CONFIG *new; const FSPM_CONFIG *new;
const FSP_M_CONFIG *old; const FSPM_CONFIG *old;
old = &fspm_old_upd->FspmConfig; old = &fspm_old_upd->FspmConfig;
new = &fspm_new_upd->FspmConfig; new = &fspm_new_upd->FspmConfig;

112
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
View File

@ -35,6 +35,14 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h> #include <FspUpd.h>
/*
* Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
* Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
* is that they will converge to use FSPM_CONFIG over time. So both will
* co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
*/
#define FSP_M_CONFIG FSPM_CONFIG
#define SPEED_REC_96GT 0 #define SPEED_REC_96GT 0
#define SPEED_REC_104GT 1 #define SPEED_REC_104GT 1
#define ADAPTIVE_CTLE 0x3f #define ADAPTIVE_CTLE 0x3f
@ -452,207 +460,217 @@ typedef struct {
**/ **/
UINT8 KtiInEnableMktme; UINT8 KtiInEnableMktme;
/** Offset 0x00BC - IIO ConfigIOU0 /** Offset 0x00BC - Usage type for Processor VmxEnable Function
Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00
$EN_DIS
**/
UINT8 VmxEnable;
/** Offset 0x00BD - IIO ConfigIOU0
ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
$EN_DIS
**/ **/
UINT8 IioConfigIOU0[8]; UINT8 IioConfigIOU0[8];
/** Offset 0x00C4 - IIO ConfigIOU1 /** Offset 0x00C5 - IIO ConfigIOU1
ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/ **/
UINT8 IioConfigIOU1[8]; UINT8 IioConfigIOU1[8];
/** Offset 0x00CC - IIO ConfigIOU2 /** Offset 0x00CD - IIO ConfigIOU2
ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/ **/
UINT8 IioConfigIOU2[8]; UINT8 IioConfigIOU2[8];
/** Offset 0x00D4 - IIO ConfigIOU3 /** Offset 0x00D5 - IIO ConfigIOU3
ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/ **/
UINT8 IioConfigIOU3[8]; UINT8 IioConfigIOU3[8];
/** Offset 0x00DC - IIO ConfigIOU4 /** Offset 0x00DD - IIO ConfigIOU4
ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/ **/
UINT8 IioConfigIOU4[8]; UINT8 IioConfigIOU4[8];
/** Offset 0x00E4 - Usage type for IIO PCIE Config Table Ptr /** Offset 0x00E5
**/
UINT8 UnusedUpdSpace3[3];
/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr
IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr
**/ **/
UINT32 IioPcieConfigTablePtr; UINT32 IioPcieConfigTablePtr;
/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Number /** Offset 0x00EC - Usage type for IIO PCIE Config Table Number
IIO PCIE Config Table Number IIO PCIE Config Table Number
**/ **/
UINT32 IioPcieConfigTableNumber; UINT32 IioPcieConfigTableNumber;
/** Offset 0x00EC - Usage type for IIO PCIE Root Port Enable or Disable /** Offset 0x00F0 - Usage type for IIO PCIE Root Port Enable or Disable
IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
the value is 0x00 the value is 0x00
**/ **/
UINT8 IIOPcieRootPortEnable; UINT8 IIOPcieRootPortEnable;
/** Offset 0x00ED - Usage type for IIO DeEmphasis /** Offset 0x00F1 - Usage type for IIO DeEmphasis
IIO DeEmphasis IIO DeEmphasis
**/ **/
UINT8 DeEmphasis; UINT8 DeEmphasis;
/** Offset 0x00EE - Usage type for IIO PCIE Root Port link speed /** Offset 0x00F2 - Usage type for IIO PCIE Root Port link speed
IIO root port link speed IIO root port link speed
**/ **/
UINT8 IIOPciePortLinkSpeed; UINT8 IIOPciePortLinkSpeed;
/** Offset 0x00EF - Usage type for IIO PCIE Root Port Max Payload /** Offset 0x00F3 - Usage type for IIO PCIE Root Port Max Payload
IIO Root Port Max Payload IIO Root Port Max Payload
**/ **/
UINT8 IIOPcieMaxPayload; UINT8 IIOPcieMaxPayload;
/** Offset 0x00F0 - Usage type for IIO DfxDnTxPreset /** Offset 0x00F4 - Usage type for IIO DfxDnTxPreset
IIO DfxDnTxPreset IIO DfxDnTxPreset
**/ **/
UINT8 DfxDnTxPreset; UINT8 DfxDnTxPreset;
/** Offset 0x00F1 - Usage type for IIO DfxRxPreset /** Offset 0x00F5 - Usage type for IIO DfxRxPreset
IIO DfxRxPreset IIO DfxRxPreset
**/ **/
UINT8 DfxRxPreset; UINT8 DfxRxPreset;
/** Offset 0x00F2 - Usage type for IIO DfxUpTxPreset /** Offset 0x00F6 - Usage type for IIO DfxUpTxPreset
IIO DfxUpTxPreset IIO DfxUpTxPreset
**/ **/
UINT8 DfxUpTxPreset; UINT8 DfxUpTxPreset;
/** Offset 0x00F3 - Usage type for IIO PcieCommonClock /** Offset 0x00F7 - Usage type for IIO PcieCommonClock
IIO PcieCommonClock IIO PcieCommonClock
**/ **/
UINT8 PcieCommonClock; UINT8 PcieCommonClock;
/** Offset 0x00F4 - Usage type for IIO NtbPpd /** Offset 0x00F8 - Usage type for IIO NtbPpd
IIO NtbPpd IIO NtbPpd
**/ **/
UINT8 NtbPpd; UINT8 NtbPpd;
/** Offset 0x00F5 - Usage type for IIO NtbBarSizeOverride /** Offset 0x00F9 - Usage type for IIO NtbBarSizeOverride
IIO NtbBarSizeOverride IIO NtbBarSizeOverride
**/ **/
UINT8 NtbBarSizeOverride; UINT8 NtbBarSizeOverride;
/** Offset 0x00F6 - Usage type for IIO NtbSplitBar /** Offset 0x00FA - Usage type for IIO NtbSplitBar
IIO NtbSplitBar IIO NtbSplitBar
**/ **/
UINT8 NtbSplitBar; UINT8 NtbSplitBar;
/** Offset 0x00F7 - Usage type for IIO NtbBarSizeImBar1 /** Offset 0x00FB - Usage type for IIO NtbBarSizeImBar1
IIO NtbBarSizeImBar1 IIO NtbBarSizeImBar1
**/ **/
UINT8 NtbBarSizeImBar1; UINT8 NtbBarSizeImBar1;
/** Offset 0x00F8 - Usage type for IIO NtbBarSizeImBar2 /** Offset 0x00FC - Usage type for IIO NtbBarSizeImBar2
IIO PNtbBarSizeImBar2 IIO PNtbBarSizeImBar2
**/ **/
UINT8 NtbBarSizeImBar2; UINT8 NtbBarSizeImBar2;
/** Offset 0x00F9 - Usage type for IIO NtbBarSizeImBar2_0 /** Offset 0x00FD - Usage type for IIO NtbBarSizeImBar2_0
IIO PNtbBarSizeImBar2_0 IIO PNtbBarSizeImBar2_0
**/ **/
UINT8 NtbBarSizeImBar2_0; UINT8 NtbBarSizeImBar2_0;
/** Offset 0x00FA - Usage type for IIO NtbBarSizeImBar2_1 /** Offset 0x00FE - Usage type for IIO NtbBarSizeImBar2_1
IIO NtbBarSizeImBar2_1 IIO NtbBarSizeImBar2_1
**/ **/
UINT8 NtbBarSizeImBar2_1; UINT8 NtbBarSizeImBar2_1;
/** Offset 0x00FB - Usage type for IIO NtbBarSizeEmBarSZ1 /** Offset 0x00FF - Usage type for IIO NtbBarSizeEmBarSZ1
IIO NtbBarSizeEmBarSZ1 IIO NtbBarSizeEmBarSZ1
**/ **/
UINT8 NtbBarSizeEmBarSZ1; UINT8 NtbBarSizeEmBarSZ1;
/** Offset 0x00FC - Usage type for IIO NtbBarSizeEmBarSZ2 /** Offset 0x0100 - Usage type for IIO NtbBarSizeEmBarSZ2
IIO NtbBarSizeEmBarSZ2 IIO NtbBarSizeEmBarSZ2
**/ **/
UINT8 NtbBarSizeEmBarSZ2; UINT8 NtbBarSizeEmBarSZ2;
/** Offset 0x00FD - Usage type for IIO NtbBarSizeEmBarSZ2_0 /** Offset 0x0101 - Usage type for IIO NtbBarSizeEmBarSZ2_0
IIO NtbBarSizeEmBarSZ2_0 IIO NtbBarSizeEmBarSZ2_0
**/ **/
UINT8 NtbBarSizeEmBarSZ2_0; UINT8 NtbBarSizeEmBarSZ2_0;
/** Offset 0x00FE - Usage type for IIO NtbBarSizeEmBarSZ2_1 /** Offset 0x0102 - Usage type for IIO NtbBarSizeEmBarSZ2_1
IIO NtbBarSizeEmBarSZ2_1 IIO NtbBarSizeEmBarSZ2_1
**/ **/
UINT8 NtbBarSizeEmBarSZ2_1; UINT8 NtbBarSizeEmBarSZ2_1;
/** Offset 0x00FF - Usage type for IIO NtbXlinkCtlOverride /** Offset 0x0103 - Usage type for IIO NtbXlinkCtlOverride
IIO NtbXlinkCtlOverride IIO NtbXlinkCtlOverride
**/ **/
UINT8 NtbXlinkCtlOverride; UINT8 NtbXlinkCtlOverride;
/** Offset 0x0100 - PchSirqMode /** Offset 0x0104 - Usage type for IIO VT-D Function
IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00
**/
UINT8 VtdSupport;
/** Offset 0x0105 - PchSirqMode
Enable or Disable PchSirqMode Enable or Disable PchSirqMode
**/ **/
UINT8 PchSirqMode; UINT8 PchSirqMode;
/** Offset 0x0101 - PchAdrEn /** Offset 0x0106 - PchAdrEn
Enable or Disable PchAdr Enable or Disable PchAdr
**/ **/
UINT8 PchAdrEn; UINT8 PchAdrEn;
/** Offset 0x0102 - } TYPE:{Combo /** Offset 0x0107 - } TYPE:{Combo
Root port swapping based on device connection status : TRUE or FALSE Root port swapping based on device connection status : TRUE or FALSE
TRUE : 0x01, FALSE : 0x00 TRUE : 0x01, FALSE : 0x00
**/ **/
UINT8 PchPcieRootPortFunctionSwap; UINT8 PchPcieRootPortFunctionSwap;
/** Offset 0x0103 - PCH PCIE PLL Ssc /** Offset 0x0108 - PCH PCIE PLL Ssc
Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC
of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF
**/ **/
UINT8 PchPciePllSsc; UINT8 PchPciePllSsc;
/** Offset 0x0104 - Usage type for PCH PCIE Root Port Index /** Offset 0x0109 - Usage type for PCH PCIE Root Port Index
Index assigned to every PCH PCIE Root Port Index assigned to every PCH PCIE Root Port
**/ **/
UINT8 PchPciePortIndex[20]; UINT8 PchPciePortIndex[20];
/** Offset 0x0118 - Usage type for PCH PCIE Root Port Enable or Disable /** Offset 0x011D - Usage type for PCH PCIE Root Port Enable or Disable
0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
the value is 0x00 the value is 0x00
**/ **/
UINT8 PchPcieForceEnable[20]; UINT8 PchPcieForceEnable[20];
/** Offset 0x012C - Usage type for PCH PCIE Root Port Link Speed /** Offset 0x0131 - Usage type for PCH PCIE Root Port Link Speed
0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie
Gen2 Speed, 0x03 : Pcie Gen3 Speed Gen2 Speed, 0x03 : Pcie Gen3 Speed
**/ **/
UINT8 PchPciePortLinkSpeed[20]; UINT8 PchPciePortLinkSpeed[20];
/** Offset 0x0140 - SerialIoUartDebugEnable /** Offset 0x0145 - SerialIoUartDebugEnable
Enable SerialIo Uart debug library in FSP. Enable SerialIo Uart debug library in FSP.
0:Disable, 1:Enable 0:Disable, 1:Enable
**/ **/
UINT8 SerialIoUartDebugEnable; UINT8 SerialIoUartDebugEnable;
/** Offset 0x0141 /** Offset 0x0146 - ISA Serial Base selection
**/
UINT8 UnusedUpdSpace3;
/** Offset 0x0142 - ISA Serial Base selection
Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
0x3F8, 0x2F8 0x3F8, 0x2F8
**/ **/
UINT16 SerialIoUartDebugIoBase; UINT16 SerialIoUartDebugIoBase;
/** Offset 0x0144 /** Offset 0x0148
**/ **/
UINT8 ReservedMemoryInitUpd[16]; UINT8 ReservedMemoryInitUpd[16];
} FSP_M_CONFIG; } FSPM_CONFIG;
/** Fsp M UPD Configuration /** Fsp M UPD Configuration
**/ **/
@ -668,13 +686,13 @@ typedef struct {
/** Offset 0x0040 /** Offset 0x0040
**/ **/
FSP_M_CONFIG FspmConfig; FSPM_CONFIG FspmConfig;
/** Offset 0x0154 /** Offset 0x0158
**/ **/
UINT8 UnusedUpdSpace4[2]; UINT8 UnusedUpdSpace4[6];
/** Offset 0x0156 /** Offset 0x015E
**/ **/
UINT16 UpdTerminator; UINT16 UpdTerminator;
} FSPM_UPD; } FSPM_UPD;

23
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
View File

@ -155,6 +155,7 @@ typedef struct {
uint8_t PcieSegment; uint8_t PcieSegment;
UINT64_STRUCT SegMmcfgBase; UINT64_STRUCT SegMmcfgBase;
uint16_t stackPresentBitmap; uint16_t stackPresentBitmap;
uint16_t CxlPresentBitmap;
uint16_t M2PciePresentBitmap; uint16_t M2PciePresentBitmap;
uint8_t TotM3Kti; uint8_t TotM3Kti;
uint8_t TotCha; uint8_t TotCha;
@ -199,20 +200,23 @@ typedef struct _STACK_RES {
uint8_t Personality; // see STACK_TYPE for details uint8_t Personality; // see STACK_TYPE for details
uint8_t BusBase; uint8_t BusBase;
uint8_t BusLimit; uint8_t BusLimit;
uint16_t PciResourceIoBase; uint16_t IoBase; // Base of IO configured for this stack
uint16_t PciResourceIoLimit; uint16_t IoLimit; // Limit of IO configured for this stack
uint32_t IoApicBase; uint32_t IoApicBase; // Base of IO configured for this stack
uint32_t IoApicLimit; uint32_t IoApicLimit; // Limit of IO configured for this stack
uint32_t Mmio32Base; uint32_t Mmio32Base;
uint32_t Mmio32Limit; uint32_t Mmio32Limit;
uint64_t Mmio64Base; uint64_t Mmio64Base;
uint64_t Mmio64Limit; uint64_t Mmio64Limit;
uint8_t PciResourceBusBase; // Base of Bus resource available for PCI devices
uint8_t PciResourceBusLimit; // Limit of Bus resource available for PCI devices
uint16_t PciResourceIoBase; // Base of IO resource available for PCI devices
uint16_t PciResourceIoLimit; // Limit of IO resource available for PCI devices
uint32_t PciResourceMem32Base; uint32_t PciResourceMem32Base;
uint32_t PciResourceMem32Limit; uint32_t PciResourceMem32Limit;
uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Base;
uint64_t PciResourceMem64Limit; uint64_t PciResourceMem64Limit;
uint32_t VtdBarAddress; uint32_t VtdBarAddress;
uint32_t Slt2HfiBarAddress; // KNH Only
} STACK_RES; } STACK_RES;
typedef struct { typedef struct {
@ -224,10 +228,10 @@ typedef struct {
uint16_t PciResourceIoLimit; uint16_t PciResourceIoLimit;
uint32_t IoApicBase; uint32_t IoApicBase;
uint32_t IoApicLimit; uint32_t IoApicLimit;
uint32_t PciResourceMem32Base; uint32_t Mmio32Base;
uint32_t PciResourceMem32Limit; uint32_t Mmio32Limit;
uint64_t PciResourceMem64Base; uint64_t Mmio64Base;
uint64_t PciResourceMem64Limit; uint64_t Mmio64Limit;
STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
uint32_t RcBaseAddress; uint32_t RcBaseAddress;
IIO_DMI_PCIE_INFO PcieInfo; IIO_DMI_PCIE_INFO PcieInfo;
@ -275,7 +279,6 @@ typedef struct {
uint8_t DmiVc1; uint8_t DmiVc1;
uint8_t DmiVcm; uint8_t DmiVcm;
uint32_t CpuPCPSInfo; uint32_t CpuPCPSInfo;
uint8_t MctpEn;
uint8_t cpuSubType; uint8_t cpuSubType;
uint8_t SystemRasType; uint8_t SystemRasType;
uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC