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mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation 

- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8

BUG=b:204844399
TEST=USE="project_primus emerge-brya coreboot" and verified
     the setting meets the audible noise specification

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2021-12-13 10:46:46 +08:00 committed by Felix Held
parent 1b66bbaf83
commit 0ccb7b2d48
2 changed files with 12 additions and 0 deletions
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6
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -35,6 +35,12 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
register "MaxDramSpeed" = "3733"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+

6
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -35,6 +35,12 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
register "MaxDramSpeed" = "3733"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+