intel/fsp_broadwell_de: Add timestamp functionality

Add a little code to enable timestamps on FSP based implementation
of Broadwell-DE. I have tested it by reading back the timestamps
with cbmem utility once the board has booted into Lubuntu.

Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Werner Zeh 2017-10-10 12:29:53 +02:00 committed by Martin Roth
parent 0315b6740a
commit 0ccc3c49e4
3 changed files with 34 additions and 0 deletions

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@ -16,6 +16,7 @@ ramstage-y += cpu.c
ramstage-y += chip.c ramstage-y += chip.c
ramstage-y += northcluster.c ramstage-y += northcluster.c
ramstage-y += ramstage.c ramstage-y += ramstage.c
ramstage-y += tsc_freq.c
romstage-y += memmap.c romstage-y += memmap.c
ramstage-y += memmap.c ramstage-y += memmap.c
ramstage-y += southcluster.c ramstage-y += southcluster.c
@ -24,11 +25,13 @@ ramstage-y += reset.c
ramstage-y += acpi.c ramstage-y += acpi.c
ramstage-y += smbus_common.c ramstage-y += smbus_common.c
ramstage-y += smbus.c ramstage-y += smbus.c
romstage-y += tsc_freq.c
ramstage-y += smi.c ramstage-y += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include
CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp

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@ -26,4 +26,7 @@
#define TSEG_BASE 0xa8 /* TSEG base */ #define TSEG_BASE 0xa8 /* TSEG base */
#define TSEG_LIMIT 0xac /* TSEG limit */ #define TSEG_LIMIT 0xac /* TSEG limit */
/* CPU bus clock is fixed at 100MHz */
#define CPU_BCLK 100
#endif /* _SOC_BROADWELL_DE_H_ */ #endif /* _SOC_BROADWELL_DE_H_ */

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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <soc/msr.h>
#include <soc/broadwell_de.h>
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
platform_info = rdmsr(MSR_PLATFORM_INFO);
return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);
}