mb/kontron/bsl6: Add new Skylake COMe module
Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. The plain bSL6 variant received little testing and only during early development. The Boxer26 variant is actively used and fully tested. The latest rebase was boot tested with FILO and Linux 4.19. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29480 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
Nico Huber
parent
e0e28908d2
commit
0ccfa6805f
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_KONTRON_BSL6 || BOARD_SIEMENS_BOXER26
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select SOC_INTEL_SKYLAKE
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select SKYLAKE_SOC_PCH_H
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select EXCLUDE_NATIVE_SD_INTERFACE
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select NO_FADT_8042
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select HAVE_ACPI_RESUME if BOARD_KONTRON_BSL6
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select MAINBOARD_HAS_LPC_TPM
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select EC_KONTRON_KEMPLD
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select MAINBOARD_HAS_LIBGFXINIT
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select DRIVERS_I2C_NCT7802Y
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select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_BOXER26
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select SECUNET_DMI if BOARD_SIEMENS_BOXER26
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config MAINBOARD_DIR
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string
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default "kontron/bsl6"
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config MAINBOARD_VENDOR
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string
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default "Siemens" if BOARD_SIEMENS_BOXER26
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config MAINBOARD_PART_NUMBER
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string
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default "bSL6" if BOARD_KONTRON_BSL6
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default "Boxer26" if BOARD_SIEMENS_BOXER26
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config VARIANT_DIR
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string
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default "bsl6" if BOARD_KONTRON_BSL6
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default "boxer26" if BOARD_SIEMENS_BOXER26
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config CBFS_SIZE
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hex
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default 0x600000 if BOARD_SIEMENS_BOXER26
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config MAX_CPUS
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int
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default 8
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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endif
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@ -0,0 +1,5 @@
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config BOARD_KONTRON_BSL6
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bool "COMe-bSL6"
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config BOARD_SIEMENS_BOXER26
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bool "COMe-bSL6 on Siemens/Boxer26"
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@ -0,0 +1,9 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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Vendor name: Kontron
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Board name: COMe-bSL6
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Category: misc
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <ec/kontron/kempld/kempld.h>
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void bootblock_mainboard_early_init(void)
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{
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kempld_enable_uart_for_console();
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}
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@ -0,0 +1,10 @@
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debug_level=Debug
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hyper_threading=Enable
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power_on_after_fail=Enable
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boot_devices=(hd0,0);(hd1,0)
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boot_default=0xff
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cmos_defaults_loaded=No
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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0 120 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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# coreboot config options: pch
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408 2 e 4 power_on_after_fail
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# coreboot config options: mainboard
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440 1 e 2 ethernet1
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441 1 e 2 ethernet2
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442 1 e 2 ethernet3
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# payload config options
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512 256 s 0 boot_devices
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768 8 h 0 boot_default
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776 1 e 1 cmos_defaults_loaded
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 No
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1 1 Yes
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2 0 Disable
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2 1 Enable
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3 1 Emergency
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3 2 Alert
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3 3 Critical
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3 4 Error
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3 5 Warning
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3 6 Notice
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3 7 Info
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3 8 Debug
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3 9 Spew
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4 0 Disable
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4 1 Enable
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4 2 Keep
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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@ -0,0 +1,150 @@
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "speed_shift_enable" = "1"
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
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register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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register "PmConfigPciClockRun" = "1"
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register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
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# VR Settings Configuration for 2 Domains
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#+----------------+-------+-------+
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#| Domain/Setting | VCC | VCCGT |
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#+----------------+-------+-------+
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#| Psi1Threshold | 20A | 20A |
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#| Psi2Threshold | 5A | 5A |
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#| Psi3Threshold | 1A | 1A |
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#| Psi3Enable | 1 | 1 |
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#| Psi4Enable | 1 | 1 |
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#| ImonSlope | 0 | 0 |
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#| ImonOffset | 0 | 0 |
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#| IccMax | 55A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V |
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#| AcLoadline | 2.1 | 3.1 |
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#| DcLoadline | 2.1 | 3.1 |
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#+----------------+-------+-------+
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(55),
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.voltage_limit = 1520,
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.ac_loadline = 210,
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.dc_loadline = 210,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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.ac_loadline = 310,
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.dc_loadline = 310,
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}"
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# Vendor set Psys Pmax to 30W
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register "power_limits_config" = "{
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.psys_pmax = 30,
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}"
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# TODO
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 08.0 on end # Gaussian Mixture Model
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device pci 14.0 on # USB xHCI
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register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"
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register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"
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register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on # SATA
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register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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# SataPortsDevSlp not supported
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end
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device pci 19.0 off end # UART #2
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9 (COMe 0)
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register "PcieRpEnable[8]" = "1"
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end
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device pci 1d.1 on # PCI Express Port 10 (COMe 1)
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register "PcieRpEnable[9]" = "1"
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end
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device pci 1d.2 on # PCI Express Port 11 (COMe 2)
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register "PcieRpEnable[10]" = "1"
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end
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# EC/kempld at 0xa80/0xa81
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register "gen1_dec" = "0x00000a81"
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/kontron/kempld
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register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }"
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device generic 0.0 on end # UART #0
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on # SMBus
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chip drivers/i2c/nct7802y
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device i2c 0x2e on end
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end
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end
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 on end # GbE
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end
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end
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <soc/intel/skylake/acpi/platform.asl>
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1),
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PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1),
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PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1),
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PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1),
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PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1),
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PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF),
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PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1),
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PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1),
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PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF),
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PAD_CFG_GPO(GPP_A12, 1, PLTRST),
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1),
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PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF),
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PAD_CFG_GPO(GPP_A20, 1, DEEP),
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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PAD_CFG_GPO(GPP_A22, 1, DEEP),
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF),
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_B6, 1, DEEP),
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PAD_CFG_GPO(GPP_B7, 1, DEEP),
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PAD_CFG_GPO(GPP_B8, 1, DEEP),
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PAD_CFG_GPO(GPP_B9, 1, DEEP),
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PAD_CFG_GPO(GPP_B10, 1, DEEP),
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PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1),
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PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF),
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PAD_CFG_GPO(GPP_B17, 1, DEEP),
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PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF),
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PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PU, DEEP),
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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PAD_CFG_GPI_ACPI_SCI(GPP_C2, NONE, DEEP, YES),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF),
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/* XXX: C6 not readable */
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/* XXX: C7 not readable */
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PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF),
|
||||
PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1),
|
||||
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF),
|
||||
PAD_CFG_GPO(GPP_D3, 1, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF),
|
||||
PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL),
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL),
|
||||
PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D21, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D22, 0, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF),
|
||||
|
||||
PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1),
|
||||
PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL),
|
||||
PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_E7, NONE, DEEP, YES),
|
||||
PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
|
||||
PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF),
|
||||
PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, NONE),
|
||||
PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
|
||||
PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST),
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F18, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F22, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F23, 1, DEEP),
|
||||
|
||||
PAD_CFG_GPO(GPP_G0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_G1, 1, PLTRST),
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL),
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL),
|
||||
PAD_CFG_GPO(GPP_G4, 1, DEEP),
|
||||
PAD_CFG_GPI_APIC(GPP_G5, NONE, PLTRST),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, PLTRST, YES),
|
||||
PAD_CFG_GPO(GPP_G7, 1, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, PLTRST, YES),
|
||||
PAD_CFG_GPO(GPP_G13, 1, PLTRST),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, PLTRST, YES),
|
||||
PAD_CFG_GPO(GPP_G15, 0, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST),
|
||||
PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI_APIC(GPP_G20, NONE, PLTRST),
|
||||
PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES),
|
||||
PAD_CFG_GPO(GPP_G22, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_G23, 1, PLTRST),
|
||||
|
||||
PAD_CFG_GPO(GPP_H0, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H4, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H5, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 1, DEEP),
|
||||
PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST),
|
||||
PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST),
|
||||
PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST),
|
||||
PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
|
||||
PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPO(GPP_H23, 0, DEEP),
|
||||
|
||||
PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF),
|
||||
PAD_CFG_GPO(GPD1, 0, PWROK),
|
||||
PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 1, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
|
||||
PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <spd_bin.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <fsp/soc_binding.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
#include "variant.h"
|
||||
|
||||
/* Rcomp resistor */
|
||||
static const u16 rcomp_resistors[3] = { 121, 75, 100 };
|
||||
|
||||
/* Rcomp target */
|
||||
static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 };
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
FSP_M_CONFIG *const memory_params = &mupd->FspmConfig;
|
||||
struct spd_block blk = {
|
||||
.addr_map = { 0x50, 0x52 },
|
||||
};
|
||||
|
||||
assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors));
|
||||
assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets));
|
||||
|
||||
memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
|
||||
get_spd_smbus(&blk);
|
||||
memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0];
|
||||
memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1];
|
||||
|
||||
memcpy(memory_params->RcompResistor, rcomp_resistors,
|
||||
sizeof(memory_params->RcompResistor));
|
||||
memcpy(memory_params->RcompTarget, rcomp_targets,
|
||||
sizeof(memory_params->RcompTarget));
|
||||
|
||||
memory_params->DqPinsInterleaved = true;
|
||||
|
||||
get_option(&memory_params->HyperThreading, "hyper_threading");
|
||||
|
||||
variant_memory_init_params(mupd);
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List := (DP2, HDMI2, others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
|
||||
register "SkipExtGfxScan" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 1c.0 off end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1f.0 on
|
||||
chip ec/kontron/kempld
|
||||
device generic 1.0 on # I2C
|
||||
chip drivers/i2c/lm96000
|
||||
register "vin[1].low" = "1140*100/116"
|
||||
register "vin[1].high" = "1260*100/116"
|
||||
register "vin[0].low" = "1810"
|
||||
register "vin[0].high" = "2000"
|
||||
register "vin[2].low" = "3140"
|
||||
register "vin[2].high" = "3470"
|
||||
register "vin[3].low" = "4750"
|
||||
register "vin[3].high" = "5250"
|
||||
register "vin[4].low" = "11400"
|
||||
register "vin[4].high" = "12600"
|
||||
|
||||
register "fan_in[0].low" = "3240"
|
||||
register "fan_in[1].low" = "3240"
|
||||
|
||||
register "fan[0].mode" = "LM96000_FAN_MANUAL"
|
||||
register "fan[0].spinup" = "LM96000_SPINUP_250MS"
|
||||
register "fan[0].freq" = "LM96000_PWM_25_7KHZ"
|
||||
register "fan[0].duty_cycle" = "100"
|
||||
|
||||
register "fan[1].mode" = "LM96000_FAN_MANUAL"
|
||||
register "fan[1].spinup" = "LM96000_SPINUP_250MS"
|
||||
register "fan[1].freq" = "LM96000_PWM_25_7KHZ"
|
||||
register "fan[1].duty_cycle" = "100"
|
||||
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
chip drivers/secunet/dmi
|
||||
device i2c 0x57 on end # Serial EEPROM
|
||||
end
|
||||
end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/nct7802y
|
||||
register "fan[1].mode" = "FAN_MANUAL"
|
||||
register "fan[1].duty_cycle" = "100"
|
||||
end
|
||||
end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 on end # GbE # Debug
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *const mupd)
|
||||
{
|
||||
char nvram_var[] = "ethernetx";
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < 3; ++i) {
|
||||
u8 eth_enable = 1;
|
||||
nvram_var[sizeof(nvram_var) - 2] = '1' + i;
|
||||
get_option(ð_enable, nvram_var);
|
||||
if (!eth_enable) {
|
||||
printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i);
|
||||
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP1,
|
||||
DP2,
|
||||
DP3,
|
||||
HDMI1,
|
||||
HDMI2,
|
||||
HDMI3,
|
||||
eDP,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
# Enable Root port 1..4 (COMe 4..7), 12 (COMe 3)
|
||||
register "PcieRpEnable[ 0]" = "1"
|
||||
register "PcieRpEnable[ 1]" = "1"
|
||||
register "PcieRpEnable[ 2]" = "1"
|
||||
register "PcieRpEnable[ 3]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
|
||||
register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC4)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
|
||||
register "SataPortsEnable[3]" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 on end # PCI Express Port 2
|
||||
device pci 1c.2 on end # PCI Express Port 3
|
||||
device pci 1c.3 on end # PCI Express Port 4
|
||||
device pci 1d.3 on end # PCI Express Port 12
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/nct7802y
|
||||
register "peci[0]" = "{ PECI_DOMAIN_0, 100 }"
|
||||
register "fan[1].mode" = "FAN_SMART"
|
||||
register "fan[1].smart.mode" = "SMART_FAN_DUTY"
|
||||
register "fan[1].smart.tempsrc" = "TEMP_SOURCE_PECI_0"
|
||||
register "fan[1].smart.table" = "{ { 30, 40 },
|
||||
{ 40, 48 },
|
||||
{ 50, 60 },
|
||||
{ 60, 76 } }"
|
||||
register "fan[1].smart.critical_temp" = "80"
|
||||
end
|
||||
end # SMBus
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *const mupd)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue