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Remove non-ascii & unprintable characters 

These non-ascii & unprintable characters aren't needed.

Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2016-07-29 14:07:30 -06:00 committed by Stefan Reinauer
parent bb9722bd77
commit 0cd338e6e4
46 changed files with 114 additions and 114 deletions
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6
src/arch/x86/acpigen.c
View File

@ -222,9 +222,9 @@ void acpigen_write_string(const char *string)
/*
* The naming conventions for ACPI namespace names are a bit tricky as
* each element has to be 4 chars wide (»All names are a fixed 32 bits.«)
* and »By convention, when an ASL compiler pads a name shorter than 4
* characters, it is done so with trailing underscores (‘_’).«.
* each element has to be 4 chars wide ("All names are a fixed 32 bits.")
* and "By convention, when an ASL compiler pads a name shorter than 4
* characters, it is done so with trailing underscores ('_')".
*
* Check sections 5.3, 18.2.2 and 18.4 of ACPI spec 3.0 for details.
*/

2
src/arch/x86/smbios.c
View File

@ -16,7 +16,7 @@
*/
/*
* Standard Manufacturer’s Identification Code
* Standard Manufacturer's Identification Code
* JEP106AS (Revision of JEP106AR, October 2015)
* MAY 2016
* http://www.jedec.org/standards-documents/results/JEP106AS

6
src/cpu/allwinner/a10/twi.c
View File

@ -14,9 +14,9 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs
* Setup helpers for Two Wire Interface (TWI) (I2C) Allwinner CPUs
*
* Only functionality for I²C master is provided.
* Only functionality for I2C master is provided.
* Largely based on the uboot-sunxi code.
*/
@ -63,7 +63,7 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
/* Enable the I2C bus */
write32(&twi->ctl, TWI_CTL_BUS_EN);
/* Issue soft reset */
write32(&twi->reset, 1);

2
src/cpu/allwinner/a10/twi.h
View File

@ -13,7 +13,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs
* Definitions Two Wire Interface (TWI) (I2C) Allwinner CPUs
*/
#ifndef CPU_ALLWINNER_A10_TWI_H

2
src/cpu/intel/slot_1/l2_cache.c
View File

@ -339,7 +339,7 @@ int test_l2_address_alias(u32 address1, u32 address2,
/* Calculates the L2 cache size.
*
* Reference: Intel(R) 64 and IA-32 Architectures Software Developer<EFBFBD>s Manual
* Reference: Intel(R) 64 and IA-32 Architectures Software Developer's Manual
* Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172.
*
*/

18
src/drivers/xpowers/axp209/axp209.c
View File

@ -44,7 +44,7 @@ enum registers {
* in one transaction.
* These return the number of bytes read/written, or an error code. In this
* case, they return 1 on success, or an error code otherwise. This is done to
* work with I²C drivers that return either 0 on success or the number of bytes
* work with I2C drivers that return either 0 on success or the number of bytes
* actually transferred.
*/
static int axp209_read(u8 bus, u8 reg, u8 *val)
@ -62,9 +62,9 @@ static int axp209_write(u8 bus, u8 reg, u8 val)
}
/**
* \brief Identify and initialize an AXP209 on the I²C bus
* \brief Identify and initialize an AXP209 on the I2C bus
*
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on if an AXP209 is found, or an error code otherwise.
*/
enum cb_err axp209_init(u8 bus)
@ -91,7 +91,7 @@ enum cb_err axp209_init(u8 bus)
* Valid values are between 700mV and 2275mV
*
* @param[in] millivolts voltage in mV units.
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success,
* CB_ERR_ARG if voltage is out of range, or an error code otherwise.
*/
@ -118,7 +118,7 @@ enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts)
* Valid values are between 700mV and 3500mV
*
* @param[in] millivolts voltage in mV units.
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success,
* CB_ERR_ARG if voltage is out of range, or an error code otherwise.
*/
@ -145,7 +145,7 @@ enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts)
* Valid values are between 700mV and 3300mV
*
* @param[in] millivolts voltage in mV units.
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success,
* CB_ERR_ARG if voltage is out of range, or an error code otherwise.
*/
@ -179,7 +179,7 @@ enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts)
* 2250mV, but hardware samples go as high as 3500mV.
*
* @param[in] millivolts voltage in mV units.
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success,
* CB_ERR_ARG if voltage is out of range, or an error code otherwise.
*/
@ -207,7 +207,7 @@ enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts)
* Valid values are between 1250V and 3300mV
*
* @param[in] millivolts voltage in mV units.
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success,
* CB_ERR_ARG if voltage is out of range, or an error code otherwise.
*/
@ -290,7 +290,7 @@ static enum cb_err set_rail(u8 bus, int idx, u16 mv)
* reconfigured, and retain its powerup voltage.
*
* @param[in] cfg pointer to @ref drivers_xpowers_axp209_config structure
* @param[in] bus I²C bus to which the AXP209 is connected
* @param[in] bus I2C bus to which the AXP209 is connected
* @return CB_SUCCES on success, or an error code otherwise.
*/
enum cb_err axp209_set_voltages(u8 bus, const struct

2
src/ec/quanta/ene_kb3940q/acpi/battery.asl
View File

@ -67,7 +67,7 @@ Device (BATX)
Store (Zero, BFWK)
}
// Device insertion/removal control method that returns a device’s status.
// Device insertion/removal control method that returns a device's status.
// Power resource object that evaluates to the current on or off state of
// the Power Resource.
Method (_STA, 0, Serialized)

4
src/lib/tpm_error_messages.h
View File

@ -158,7 +158,7 @@ and locality modifier not part of command transport" },
{ "TPM_BAD_LOCALITY", TPM_E_BASE + 61,
"The locality is incorrect for the attempted operation" },
{ "TPM_READ_ONLY", TPM_E_BASE + 62,
"The NV area is read only and canât be written to" },
"The NV area is read only and can't be written to" },
{ "TPM_PER_NOWRITE", TPM_E_BASE + 63,
"There is no protection on the write to the NV area" },
{ "TPM_FAMILYCOUNT", TPM_E_BASE + 64,
@ -208,7 +208,7 @@ by the TPM Owner" },
"The atomic process indicated by the submitted DAA command is not\n\
the expected process" },
{ "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86,
"The issuerâs validity check has detected an inconsistency" },
"The issuer's validity check has detected an inconsistency" },
{ "TPM_DAA_WRONG_W", TPM_E_BASE + 87,
"The consistency check on w has failed" },
{ "TPM_BAD_HANDLE", TPM_E_BASE + 88,

4
src/mainboard/apple/macbook21/romstage.c
View File

@ -85,8 +85,8 @@ static void ich7_enable_lpc(void)
// Macbook21: 0x0010 == 00000000 00010000
// Bit 9:8 LPT Decode Range. This field determines which range to
// decode for the LPT Port.
// 00 = 378h ­ 37Fh and 778h ­ 77Fh
// 10 = 3BCh ­ 3BEh and 7BCh ­ 7BEh
// 00 = 378h - 37Fh and 778h - 77Fh
// 10 = 3BCh - 3BEh and 7BCh - 7BEh
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// LPC_EN--LPC I/F Enables Register

2
src/mainboard/cubietech/cubieboard/devicetree.cb
View File

@ -1,7 +1,7 @@
chip cpu/allwinner/a10
device cpu_cluster 0 on end
chip drivers/xpowers/axp209 # AXP209 is on I²C 0
chip drivers/xpowers/axp209 # AXP209 is on I2C 0
device i2c 0x34 on end
register "dcdc2_voltage_mv" = "1400" # Vcore
register "dcdc3_voltage_mv" = "1250" # DLL Vdd

2
src/mainboard/google/cosmos/chromeos.c
View File

@ -1,4 +1,4 @@
/*
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.

4
src/mainboard/google/parrot/ec.h
View File

@ -49,8 +49,8 @@
* AC power plug-out C8h
* Modem Ring In CAh
* PME signal active CEh
* Acer Hotkey Function – Make event D5h
* Acer Hotkey Function – Break event D6h
* Acer Hotkey Function - Make event D5h
* Acer Hotkey Function - Break event D6h
*/
#ifndef __ACPI__

2
src/mainboard/google/purin/chromeos.c
View File

@ -1,4 +1,4 @@
/*
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.

4
src/mainboard/google/stout/ec.c
View File

@ -48,10 +48,10 @@ void stout_ec_init(void)
* Set USB Power off in S3 (enabled in S3 path if requested in gnvs)
* Bit0 of 0x0D/Bit0 of 0x26
* 0/0 All USB port off
* 1/0 USB on, all USB port didn’t support wake up
* 1/0 USB on, all USB port didn't support wake up
* 0/1 USB on, yellow port support wake up charge, but may not support
* charge smart phone.
* 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
* 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
*/
ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE);
ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) & 0xE);

4
src/mainboard/google/stout/mainboard_smi.c
View File

@ -58,10 +58,10 @@ void mainboard_smi_sleep(u8 slp_typ)
* Tell the EC to Enable USB power for S3 if requested.
* Bit0 of 0x0D/Bit0 of 0x26
* 0/0 All USB port off
* 1/0 USB on, all USB port didn’t support wake up
* 1/0 USB on, all USB port didn't support wake up
* 0/1 USB on, yellow port support wake up charge, but may not support
* charge smart phone.
* 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
* 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
*/
if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) {
ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00);

2
src/mainboard/google/veyron/chromeos.c
View File

@ -1,4 +1,4 @@
/*
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.

2
src/mainboard/google/veyron_rialto/chromeos.c
View File

@ -1,4 +1,4 @@
/*
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.

2
src/mainboard/siemens/sitemp_g1p1/mainboard.c
View File

@ -49,7 +49,7 @@
#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz
#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01
// Callback Sub-Function 05h – Select Boot-up TV Standard
// Callback Sub-Function 05h - Select Boot-up TV Standard
#define TV_MODE_00 0x00 /* NTSC */
#define TV_MODE_01 0x01 /* PAL */
#define TV_MODE_02 0x02 /* PALM */

2
src/mainboard/technexion/tim5690/mainboard.c
View File

@ -40,7 +40,7 @@
#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
//Callback Sub-Function 05h – Select Boot-up TV Standard
//Callback Sub-Function 05h - Select Boot-up TV Standard
#define TV_MODE_00 0x00 /* NTSC */
#define TV_MODE_01 0x01 /* PAL */
#define TV_MODE_02 0x02 /* PALM */

2
src/mainboard/via/epia-m700/romstage.c
View File

@ -187,7 +187,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
/* VT3409 no PCI-E */
{ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range
{ 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie
// { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
// { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
// Set ROMSIP value by software
/*

2
src/northbridge/amd/amdfam10/acpi.c
View File

@ -129,7 +129,7 @@ static unsigned long acpi_fill_srat(unsigned long current)
static unsigned long acpi_fill_slit(unsigned long current)
{
/* Implement SLIT algorithm in BKDG Rev. 3.62 § 2.3.6.1
/* Implement SLIT algorithm in BKDG Rev. 3.62 Section 2.3.6.1
* Fill the first 8 bytes with the node number,
* then fill the next num*num byte with the distance,
* Distance entries vary with topology; the local node

2
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View File

@ -1541,7 +1541,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "+");
} else {
if (read_iter < 16)
printk(BIOS_DEBUG, "°");
printk(BIOS_DEBUG, ":");
else
printk(BIOS_DEBUG, ".");
}

4
src/northbridge/intel/e7505/raminit.c
View File

@ -1007,10 +1007,10 @@ static inline void __attribute__((always_inline))
unsigned int a1, a2;
asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::);
asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::);
printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
asm volatile("movd %%xmm0, %%eax;" : "=a" (a1) ::);
asm volatile("movd %%xmm1, %%eax;" : "=a" (a2) ::);
printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
#endif
}

2
src/northbridge/intel/gm45/pcie.c
View File

@ -289,7 +289,7 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
* Maybe we just have to advertise ASPM through LCAP[11:10]
* (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO),
* set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the
* generic ASPM code do the rest? – Nico
* generic ASPM code do the rest? - Nico
*/
/* TODO: Prepare PEG for ASPM. */
}

4
src/northbridge/intel/i82830/smihandler.c
View File

@ -166,11 +166,11 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
}
case 0x0002:
printk(BIOS_DEBUG, "|- MBI_Attach\n");
printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
printk(BIOS_DEBUG, "| |- Not Implemented!\n");
break;
case 0x0003:
printk(BIOS_DEBUG, "|- MBI_Detach\n");
printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
printk(BIOS_DEBUG, "| |- Not Implemented!\n");
break;
case 0x0201: {
obj_header_t *obj_header = (obj_header_t *)banner_id;

2
src/northbridge/intel/sandybridge/report_platform.c
View File

@ -62,7 +62,7 @@ static struct {
/* 6-series PCI ids from
* Intel® 6 Series Chipset and
* Intel® C200 Series Chipset
* Specification Update – NDA
* Specification Update - NDA
* October 2013
* CDI / IBP#: 440377
*/

4
src/northbridge/via/vx900/early_host_bus_ctl.c
View File

@ -20,9 +20,9 @@ static void vx900_cpu_bus_preram_setup(void)
{
/* Faster CPU to DRAM Cycle */
pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08);
/* CPU Interface Control – Basic Options */
/* CPU Interface Control - Basic Options */
pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c);
/*CPU Interface Control – Advanced Options */
/*CPU Interface Control - Advanced Options */
pci_write_config8(HOST_BUS, 0x52, 0xc7);
/* Enable 8QW burst and 4QW request merging [4] and [2]
* and special mode for read cycles bit[3] */

30
src/northbridge/via/vx900/raminit_ddr3.c
View File

@ -186,14 +186,14 @@ static pci_reg8 mcu_drv_ctrl_config[] = {
{0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */
{0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands */
{0xd0, 0x88}, /* (ODT) Strength ?has effect? */
{0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */
{0xe0, 0x88}, /* DRAM Driving - Group DQS (MDQS) */
{0xe1, 0x00}, /* Disable offset mode for driving strength control */
{0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */
{0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */
{0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */
{0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */
{0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */
{0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */
{0xe2, 0x88}, /* DRAM Driving - Group DQ (MD, MDQM) */
{0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */
{0xe8, 0x88}, /* DRAM Driving - Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */
{0xe6, 0xff}, /* DRAM Driving - Group DCLK0 (DCLK[2:0] for DIMM0) */
{0xe7, 0xff}, /* DRAM Driving - Group DCLK1 (DCLK[5:3] for DIMM1) */
{0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */
{0x91, 0x08}, /* MCLKO Output Phase Delay - I */
{0x92, 0x08}, /* MCLKO Output Phase Delay - II */
{0x93, 0x16}, /* CS/CKE Output Phase Delay */
@ -807,8 +807,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
/* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */
/* Step 09 – Issue MR2 cycle. Read a double word from the address
* depended on DRAM’s Rtt_WR and CWL settings. */
/* Step 09 - Issue MR2 cycle. Read a double word from the address
* depended on DRAM's Rtt_WR and CWL settings. */
mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl);
if (ma_swap)
mrs = ddr3_mrs_mirror_pins(mrs);
@ -816,7 +816,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
printram("MR2: %.5x\n", mrs);
udelay(1000);
/* Step 10 – Issue MR3 cycle. Read a double word from the address 60000h
/* Step 10 - Issue MR3 cycle. Read a double word from the address 60000h
* to set DRAM to normal operation mode. */
mrs = ddr3_get_mr3(0);
if (ma_swap)
@ -825,8 +825,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
printram("MR3: %.5x\n", mrs);
udelay(1000);
/* Step 11 –Issue MR1 cycle. Read a double word from the address
* depended on DRAM’s output driver impedance and Rtt_Nom settings.
/* Step 11 -Issue MR1 cycle. Read a double word from the address
* depended on DRAM's output driver impedance and Rtt_Nom settings.
* The DLL enable field, TDQS field, write leveling enable field,
* additive latency field and Qoff field should be set to 0. */
mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom,
@ -839,7 +839,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
udelay(1000);
/* Step 12 - Issue MR0 cycle. Read a double word from the address
* depended on DRAM’s burst length, CAS latency and write recovery time
* depended on DRAM's burst length, CAS latency and write recovery time
* settings.
* The read burst type field should be set to interleave.
* The mode field should be set to normal mode.
@ -942,13 +942,13 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
vx900_map_pr_vr(i, 3);
}
/* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
/* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
/* Set BA[0/1/2] to [A13/14/15] */
vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP);
/* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
/* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
pci_mod_config8(MCU, 0x69, 0x00, (1 << 0));
printram("DIMM initialization sequence complete\n");

6
src/northbridge/via/vx900/sata.c
View File

@ -199,7 +199,7 @@ static void vx900_sata_init(device_t dev)
/* Resend COMRESET When Recovering SATA Gen2 Device Error */
pci_mod_config8(dev, 0x62, 1 << 1, 1 << 7);
/* Fix "PMP Device Can’t Detect HDD Normally" (VIA Porting Guide)
/* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide)
* SATA device detection will not work unless we clear these bits.
* Without doing this, SeaBIOS (and potentially other payloads) will
* timeout when detecting SATA devices */
@ -211,8 +211,8 @@ static void vx900_sata_init(device_t dev)
* reset and check the BSY bit of one port only, and the BSY bit of
* other port would be 1, then it does another software reset
* immediately and causes the system hang.
* This is because the first software reset doesn’t finish, and the
* state machine of the host controller conflicts, it can’t finish the
* This is because the first software reset doesn't finish, and the
* state machine of the host controller conflicts, it can't finish the
* second one anymore. The BSY bit of slave port would be always 1 after
* the second software reset issues. BIOS should set the following
* bit to avoid this issue. */

4
src/soc/broadcom/cygnus/ddr_init.c
View File

@ -97,8 +97,8 @@ void PRE_SRX(void)
readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
// Turn on PHY_CONTROL AUTO_OEB ¨C not required
// Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL ¨C already set 180114c8: 000f000a
// Turn on PHY_CONTROL AUTO_OEB C not required
// Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a
printk(BIOS_INFO, "\n....PLL power up.\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));

6
src/soc/intel/fsp_baytrail/acpi/irqroute.asl
View File

@ -19,9 +19,9 @@ Method(_PRT)
{
/*
* PICM comes from _PIC, which returns the following:
* 0 – PIC mode
* 1 – APIC mode
* 2 – SAPIC mode
* 0 - PIC mode
* 1 - APIC mode
* 2 - SAPIC mode
*/
If (PICM) {
Return (Package() {

6
src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl
View File

@ -19,9 +19,9 @@ Method(_PRT)
{
/*
* PICM comes from _PIC, which returns the following:
* 0 – PIC mode
* 1 – APIC mode
* 2 – SAPIC mode
* 0 - PIC mode
* 1 - APIC mode
* 2 - SAPIC mode
*/
If (PICM) {
Return (Package() {

2
src/southbridge/amd/agesa/hudson/fadt.c
View File

@ -67,7 +67,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;

2
src/southbridge/amd/cimx/sb800/fadt.c
View File

@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */
fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */
fadt->smi_cmd = 0; /* disable system management mode */
fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */

2
src/southbridge/amd/pi/hudson/fadt.c
View File

@ -59,7 +59,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->dsdt = (u32) dsdt;
fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;

2
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
src/southbridge/intel/fsp_bd82x6x/smihandler.c
View File

@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
src/southbridge/intel/fsp_i89xx/smihandler.c
View File

@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

6
src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl
View File

@ -19,9 +19,9 @@ Method(_PRT)
{
/*
* PICM comes from _PIC, which returns the following:
* 0 – PIC mode
* 1 – APIC mode
* 2 – SAPIC mode
* 0 - PIC mode
* 1 - APIC mode
* 2 - SAPIC mode
*/
If (PICM) {
Return (Package() {

2
src/southbridge/intel/i82801dx/smihandler.c
View File

@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
src/southbridge/intel/i82801gx/smihandler.c
View File

@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
/* IOTRAP(0) SMIC: currently unused */
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
src/southbridge/intel/i82801ix/smihandler.c
View File

@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");

2
util/inteltool/cpu.c
View File

@ -1003,7 +1003,7 @@ int print_intel_core_msrs(void)
/*
* The following two tables are the Silvermont registers listed in Table 35-6
* Intel® 64 and IA-32 Architectures Software Developer’s Manual
* Intel® 64 and IA-32 Architectures Software Developer's Manual
* September 2014
* Vol. 3C 35-59
*/

42
util/kconfig/regex.c
View File

@ -120,7 +120,7 @@ init_syntax_once ()
#define SYNTAX(c) re_syntax_table[c]
#endif /* not emacs */
/* Get the interface, including the syntax bits. */
#include "regex.h"
@ -168,7 +168,7 @@ init_syntax_once ()
/* As in Harbison and Steele. */
#define SIGN_EXTEND_CHAR(c) ((((unsigned char) (c)) ^ 128) - 128)
#endif
/* Should we use malloc or alloca? If REGEX_MALLOC is not defined, we
use `alloca' instead of `malloc'. This is because using malloc in
re_search* or re_match* could cause memory leaks when C-g is used in
@ -236,7 +236,7 @@ char *alloca ();
typedef char boolean;
#define false 0
#define true 1
/* These are the command codes that appear in compiled regular
expressions. Some opcodes are followed by argument bytes. A
command code can specify any interpretation whatsoever for its
@ -376,7 +376,7 @@ typedef enum
notsyntaxspec
#endif /* emacs */
} re_opcode_t;
/* Common operations on the compiled pattern. */
/* Store NUMBER in two contiguous bytes starting at DESTINATION. */
@ -450,7 +450,7 @@ extract_number_and_incr (destination, source)
#endif /* not EXTRACT_MACROS */
#endif /* DEBUG */
/* If DEBUG is defined, Regex prints many voluminous messages about what
it is doing (if the variable `debug' is nonzero). If linked with the
main program in `iregex.c', you can enter patterns and strings
@ -790,7 +790,7 @@ print_double_string (where, string1, size1, string2, size2)
#define DEBUG_PRINT_DOUBLE_STRING(w, s1, sz1, s2, sz2)
#endif /* not DEBUG */
/* Set by `re_set_syntax' to the current regexp syntax to recognize. Can
also be assigned to arbitrarily: each pattern buffer stores its own
syntax, so it can be changed between regex compilations. */
@ -813,7 +813,7 @@ re_set_syntax (syntax)
re_syntax_options = syntax;
return ret;
}
/* This table gives an error message for each of the error codes listed
in regex.h. Obviously the order here has to be same as there. */
@ -836,7 +836,7 @@ static const char *re_error_msg[] =
"Regular expression too big", /* REG_ESIZE */
"Unmatched ) or \\)", /* REG_ERPAREN */
};
/* Subroutine declarations and macros for regex_compile. */
static void store_op1 (), store_op2 ();
@ -1039,7 +1039,7 @@ typedef struct
|| STREQ (string, "space") || STREQ (string, "print") \
|| STREQ (string, "punct") || STREQ (string, "graph") \
|| STREQ (string, "cntrl") || STREQ (string, "blank"))
/* `regex_compile' compiles PATTERN (of length SIZE) according to SYNTAX.
Returns one of error codes defined in `regex.h', or zero for success.
@ -2054,7 +2054,7 @@ regex_compile (pattern, size, syntax, bufp)
return REG_NOERROR;
} /* regex_compile */
/* Subroutines for `regex_compile'. */
/* Store OP at LOC followed by two-byte integer parameter ARG. */
@ -2240,7 +2240,7 @@ compile_range (p_ptr, pend, translate, syntax, b)
return REG_NOERROR;
}
/* Failure stack declarations and macros; both re_compile_fastmap and
re_match_2 use a failure stack. These have to be macros because of
REGEX_ALLOCATE. */
@ -2514,7 +2514,7 @@ typedef struct
\
DEBUG_STATEMENT (nfailure_points_popped++); \
} /* POP_FAILURE_POINT */
/* re_compile_fastmap computes a ``fastmap'' for the compiled pattern in
BUFP. A fastmap records which of the (1 << BYTEWIDTH) possible
characters can start a string that matches the pattern. This fastmap
@ -2799,7 +2799,7 @@ re_compile_fastmap (bufp)
bufp->can_be_null |= path_can_be_null;
return 0;
} /* re_compile_fastmap */
/* Set REGS to hold NUM_REGS registers, storing them in STARTS and
ENDS. Subsequent matches using PATTERN_BUFFER and REGS will use
this memory for recording register information. STARTS and ENDS
@ -2834,7 +2834,7 @@ re_set_registers (bufp, regs, num_regs, starts, ends)
regs->start = regs->end = (regoff_t) 0;
}
}
/* Searching routines. */
/* Like re_search_2, below, but only one string is specified, and
@ -2988,7 +2988,7 @@ re_search_2 (bufp, string1, size1, string2, size2, startpos, range, regs, stop)
}
return -1;
} /* re_search_2 */
/* Declarations and macros for re_match_2. */
static int bcmp_translate ();
@ -3126,7 +3126,7 @@ typedef union
to actually save any registers when none are active. */
#define NO_HIGHEST_ACTIVE_REG (1 << BYTEWIDTH)
#define NO_LOWEST_ACTIVE_REG (NO_HIGHEST_ACTIVE_REG + 1)
/* Matching routines. */
#ifndef emacs /* Emacs never uses this. */
@ -4339,7 +4339,7 @@ re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop)
return -1; /* Failure to match. */
} /* re_match_2 */
/* Subroutine definitions for re_match_2. */
@ -4601,7 +4601,7 @@ bcmp_translate (s1, s2, len, translate)
}
return 0;
}
/* Entry points for GNU code. */
/* re_compile_pattern is the GNU regular expression compiler: it
@ -4637,7 +4637,7 @@ re_compile_pattern (pattern, length, bufp)
return re_error_msg[(int) ret];
}
/* Entry points compatible with 4.2 BSD regex library. We don't define
them if this is an Emacs or POSIX compilation. */
@ -4693,7 +4693,7 @@ re_exec (s)
0 <= re_search (&re_comp_buf, s, len, 0, len, (struct re_registers *) 0);
}
#endif /* not emacs and not _POSIX_SOURCE */
/* POSIX.2 functions. Don't define these for Emacs. */
#ifndef emacs
@ -4938,7 +4938,7 @@ regfree (preg)
}
#endif /* not emacs */
/*
Local variables:
make-backup-files: t

12
util/kconfig/regex.h
View File

@ -135,7 +135,7 @@ typedef unsigned reg_syntax_t;
stored in the pattern buffer, so changing this does not affect
already-compiled regexps. */
extern reg_syntax_t re_syntax_options;
/* Define combinations of the above bits for the standard possibilities.
(The [[[ comments delimit what gets put into the Texinfo file, so
don't delete them!) */
@ -198,7 +198,7 @@ extern reg_syntax_t re_syntax_options;
| RE_NO_BK_PARENS | RE_NO_BK_REFS \
| RE_NO_BK_VBAR | RE_UNMATCHED_RIGHT_PAREN_ORD)
/* [[[end syntaxes]]] */
/* Maximum number of duplicates an interval can allow. Some systems
(erroneously) define this in other header files, but we want our
value, so remove any previous define. */
@ -268,7 +268,7 @@ typedef enum
REG_ESIZE, /* Compiled pattern bigger than 2^16 bytes. */
REG_ERPAREN /* Unmatched ) or \); not returned from regcomp. */
} reg_errcode_t;
/* This data structure represents a compiled pattern. Before calling
the pattern compiler, the fields `buffer', `allocated', `fastmap',
`translate', and `no_sub' can be set. After the pattern has been
@ -349,7 +349,7 @@ typedef struct re_pattern_buffer regex_t;
/* search.c (search_buffer) in Emacs needs this one opcode value. It is
defined both in `regex.c' and here. */
#define RE_EXACTN_VALUE 1
/* Type for byte offsets within the string. POSIX mandates this. */
typedef int regoff_t;
@ -380,7 +380,7 @@ typedef struct
regoff_t rm_so; /* Byte offset from string's start to substring's start. */
regoff_t rm_eo; /* Byte offset from string's start to substring's end. */
} regmatch_t;
/* Declarations for routines. */
/* To avoid duplicating every routine declaration -- once with a
@ -480,7 +480,7 @@ extern size_t regerror
extern void regfree _RE_ARGS ((regex_t *preg));
#endif /* not __REGEXP_LIBRARY_H__ */
/*
Local variables:
make-backup-files: t