From 0cd873f585f92de81476849f2aa1c6e1a47b26c3 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 22 Sep 2023 12:54:43 +0530
Subject: [PATCH] soc/intel/meteorlake: Reduce memory test size
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Enable upd to reduce size of the memory test.

BUG=b:301441204
TEST=Able to build and boot google/rex.

w/o this patch:

 951:returning from FspMemoryInit    650,922 (79,560)

w/ this patch:

 951:returning from FspMemoryInit    618,490 (45,621)

Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/meteorlake/chipset.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 59eb2c96d6..ce4fe08850 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -14,6 +14,9 @@ chip soc/intel/meteorlake
 		.tdp_pl4 = 120,
 	}"
 
+	# Reduce the size of BasicMemoryTests to speed up the boot time.
+	register "lower_basic_mem_test_size" = "true"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.