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soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig 

This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.

On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.

Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.

Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Uwe Poeche 2022-03-30 08:51:59 +02:00 committed by Arthur Heymans
parent ac040552fc
commit 0ce586b1a4
2 changed files with 15 additions and 3 deletions
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2
src/soc/intel/elkhartlake/include/soc/systemagent.h
View File

@ -21,7 +21,9 @@
#define VTBAR_MASK 0x7ffffff000ull #define VTBAR_MASK 0x7ffffff000ull
#define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define PKG_PWR_LIM_1_EN (1 << 15)
#define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define PKG_PWR_LIM_2_EN (1 << 15)
#define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define MCH_DDR_POWER_LIMIT_HI 0x58e4

16
src/soc/intel/elkhartlake/systemagent.c
View File

@ -48,6 +48,7 @@ void soc_systemagent_init(struct device *dev)
{ {
struct soc_power_limits_config *soc_config; struct soc_power_limits_config *soc_config;
config_t *config; config_t *config;
uint32_t value;
/* Enable Power Aware Interrupt Routing */ /* Enable Power Aware Interrupt Routing */
enable_power_aware_intr(); enable_power_aware_intr();
@ -56,7 +57,16 @@ void soc_systemagent_init(struct device *dev)
enable_bios_reset_cpl(); enable_bios_reset_cpl();
mdelay(1); mdelay(1);
config = config_of_soc(); if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
soc_config = &config->power_limits_config; printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); /* clear bits 47, 15 in PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU */
value = MCHBAR32(MCH_PKG_POWER_LIMIT_LO);
MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_PWR_LIM_1_EN);
value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI);
MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_PWR_LIM_2_EN);
} else {
config = config_of_soc();
soc_config = &config->power_limits_config;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
}
} }